diff options
| author | Christopher Covington <christopher.covington@linaro.org> | 2015-09-07 10:39:27 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-09-07 10:39:27 +0100 |
| commit | 205ace55ffff77964e50af08c99639ec47db53f6 (patch) | |
| tree | 97890823cd32a74a290804663cbe0d76ed8b557e | |
| parent | 857b55adb77004d9ec9202078b7f1f3a1a076112 (diff) | |
target-arm: Improve semihosting debug prints
Print semihosting debugging information before the
do_arm_semihosting() call so that angel_SWIreason_ReportException,
which causes the function to not return, gets the same debug prints as
other semihosting calls. Also print out the semihosting call number.
Signed-off-by: Christopher Covington <christopher.covington@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Tested-by: Christopher Covington <cov@codeaurora.org>
Message-id: 1439483745-28752-3-git-send-email-peter.maydell@linaro.org
| -rw-r--r-- | target-arm/helper.c | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 7df1f0684d..114d56e3a1 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -5228,8 +5228,10 @@ void arm_v7m_cpu_do_interrupt(CPUState *cs) nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff; if (nr == 0xab) { env->regs[15] += 2; + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%x\n", + env->regs[0]); env->regs[0] = do_arm_semihosting(env); - qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); return; } } @@ -5549,8 +5551,10 @@ void arm_cpu_do_interrupt(CPUState *cs) if (((mask == 0x123456 && !env->thumb) || (mask == 0xab && env->thumb)) && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%x\n", + env->regs[0]); env->regs[0] = do_arm_semihosting(env); - qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); return; } } @@ -5567,8 +5571,10 @@ void arm_cpu_do_interrupt(CPUState *cs) if (mask == 0xab && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { env->regs[15] += 2; + qemu_log_mask(CPU_LOG_INT, + "...handling as semihosting call 0x%x\n", + env->regs[0]); env->regs[0] = do_arm_semihosting(env); - qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n"); return; } } |