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authorPeter Maydell <peter.maydell@linaro.org>2022-11-25 11:52:36 +0000
committerPeter Maydell <peter.maydell@linaro.org>2022-12-16 15:59:07 +0000
commitbb27210c8cb8c246b221dad178a3e04566d38e3d (patch)
tree20273aba89555edf1e3e995a01478d7aa5cc5d55
parent0d898904668f806cea474077eb2b7fa53b3ef4e0 (diff)
pci: Convert TYPE_PCIE_ROOT_PORT to 3-phase reset
Convert the TYPE_PCIE_ROOT_PORT device to 3-phase reset; this is a necessary precursor to converting any of its child classes. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Tested-by: Daniel Henrique Barboza <danielhb413@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Message-id: 20221125115240.3005559-4-peter.maydell@linaro.org
-rw-r--r--hw/pci-bridge/pcie_root_port.c8
1 files changed, 5 insertions, 3 deletions
diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c
index 460e48269d..36bc0bafa7 100644
--- a/hw/pci-bridge/pcie_root_port.c
+++ b/hw/pci-bridge/pcie_root_port.c
@@ -43,9 +43,10 @@ static void rp_write_config(PCIDevice *d, uint32_t address,
pcie_aer_root_write_config(d, address, val, len, root_cmd);
}
-static void rp_reset(DeviceState *qdev)
+static void rp_reset_hold(Object *obj)
{
- PCIDevice *d = PCI_DEVICE(qdev);
+ PCIDevice *d = PCI_DEVICE(obj);
+ DeviceState *qdev = DEVICE(obj);
rp_aer_vector_update(d);
pcie_cap_root_reset(d);
@@ -171,13 +172,14 @@ static void rp_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
+ ResettableClass *rc = RESETTABLE_CLASS(klass);
k->is_bridge = true;
k->config_write = rp_write_config;
k->realize = rp_realize;
k->exit = rp_exit;
set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
- dc->reset = rp_reset;
+ rc->phases.hold = rp_reset_hold;
device_class_set_props(dc, rp_props);
}