diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2015-06-01 11:29:37 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2015-06-01 11:29:37 +0100 |
| commit | 9657cafceb90accedd574a3accb3d344def8e764 (patch) | |
| tree | d5a74748f5a485a1ecefee0e68412ee3f142b0f7 | |
| parent | 97af820f539efe80b87615a04f9de11ea585f725 (diff) | |
| parent | 07e15486faf353260431f10e85185372c5036baa (diff) | |
Merge remote-tracking branch 'remotes/bkoppelmann/tags/pull-tricore-20150530' into staging
TriCore bugfixes
# gpg: Signature made Sat May 30 15:50:49 2015 BST using RSA key ID 6B69CA14
# gpg: Good signature from "Bastian Koppelmann <kbastian@mail.uni-paderborn.de>"
* remotes/bkoppelmann/tags/pull-tricore-20150530:
target-tricore: fix BOL_ST_H_LONGOFF using ld
target-tricore: fix msub32_q producing the wrong overflow bit
target-tricore: fix OPC2_32_RR_DVINIT_HU having write before use on the result
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target-tricore/translate.c | 15 |
1 files changed, 2 insertions, 13 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index 5f8eff04fa..8d41239617 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -1980,17 +1980,6 @@ gen_msub32_q(TCGv ret, TCGv arg1, TCGv arg2, TCGv arg3, uint32_t n, tcg_gen_or_i64(t1, t1, t2); tcg_gen_trunc_i64_i32(cpu_PSW_V, t1); tcg_gen_shli_tl(cpu_PSW_V, cpu_PSW_V, 31); - /* We produce an overflow on the host if the mul before was - (0x80000000 * 0x80000000) << 1). If this is the - case, we negate the ovf. */ - if (n == 1) { - tcg_gen_setcondi_tl(TCG_COND_EQ, temp, arg2, 0x80000000); - tcg_gen_setcond_tl(TCG_COND_EQ, temp2, arg2, arg3); - tcg_gen_and_tl(temp, temp, temp2); - tcg_gen_shli_tl(temp, temp, 31); - /* negate v bit, if special condition */ - tcg_gen_xor_tl(cpu_PSW_V, cpu_PSW_V, temp); - } /* Calc SV bit */ tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); /* Calc AV/SAV bits */ @@ -5287,7 +5276,7 @@ static void decode_bol_opc(CPUTriCoreState *env, DisasContext *ctx, int32_t op1) break; case OPC1_32_BOL_ST_H_LONGOFF: if (tricore_feature(env, TRICORE_FEATURE_16)) { - gen_offset_ld(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); + gen_offset_st(ctx, cpu_gpr_d[r1], cpu_gpr_a[r2], address, MO_LESW); } else { /* raise illegal opcode trap */ } @@ -6451,8 +6440,8 @@ static void decode_rr_divide(CPUTriCoreState *env, DisasContext *ctx) /* sv */ tcg_gen_or_tl(cpu_PSW_SV, cpu_PSW_SV, cpu_PSW_V); /* write result */ - tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); tcg_gen_shli_tl(cpu_gpr_d[r3], cpu_gpr_d[r1], 16); + tcg_gen_mov_tl(cpu_gpr_d[r3+1], temp3); tcg_temp_free(temp); tcg_temp_free(temp2); tcg_temp_free(temp3); |