diff options
| author | Jingqi Liu <jingqi.liu@intel.com> | 2018-05-04 11:57:33 +0800 |
|---|---|---|
| committer | Eduardo Habkost <ehabkost@redhat.com> | 2018-05-15 11:33:33 -0300 |
| commit | 0da0fb062841d0dcd8ba47e4a989d2e952cdf0ff (patch) | |
| tree | 547888449f60dd37964bd7d33987fb8cd2365cec | |
| parent | a18495159a35e9c5973d9aa0f612a97318bf684d (diff) | |
x86/cpu: Enable CLDEMOTE(Demote Cache Line) cpu feature
The CLDEMOTE instruction hints to hardware that the cache line that
contains the linear address should be moved("demoted") from
the cache(s) closest to the processor core to a level more distant
from the processor core. This may accelerate subsequent accesses
to the line by other cores in the same coherence domain,
especially if the line was written by the core that demotes the line.
Intel Snow Ridge has added new cpu feature, CLDEMOTE.
The new cpu feature needs to be exposed to guest VM.
The bit definition:
CPUID.(EAX=7,ECX=0):ECX[bit 25] CLDEMOTE
The release document ref below link:
https://software.intel.com/sites/default/files/managed/c5/15/\
architecture-instruction-set-extensions-programming-reference.pdf
Signed-off-by: Jingqi Liu <jingqi.liu@intel.com>
Message-Id: <1525406253-54846-1-git-send-email-jingqi.liu@intel.com>
Reviewed-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
| -rw-r--r-- | target/i386/cpu.c | 2 | ||||
| -rw-r--r-- | target/i386/cpu.h | 1 |
2 files changed, 2 insertions, 1 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 52fd35b6a1..4b39ab5dd4 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -494,7 +494,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = { "avx512bitalg", NULL, "avx512-vpopcntdq", NULL, "la57", NULL, NULL, NULL, NULL, NULL, "rdpid", NULL, - NULL, NULL, NULL, NULL, + NULL, "cldemote", NULL, NULL, NULL, NULL, NULL, NULL, }, .cpuid_eax = 7, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index b58b779bff..8fbe1537c1 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -680,6 +680,7 @@ typedef uint32_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_ECX_AVX512_VPOPCNTDQ (1U << 14) /* POPCNT for vectors of DW/QW */ #define CPUID_7_0_ECX_LA57 (1U << 16) #define CPUID_7_0_ECX_RDPID (1U << 22) +#define CPUID_7_0_ECX_CLDEMOTE (1U << 25) /* CLDEMOTE Instruction */ #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) /* AVX512 Neural Network Instructions */ #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) /* AVX512 Multiply Accumulation Single Precision */ |