diff options
author | Avi Kivity <avi@redhat.com> | 2011-11-27 11:53:29 +0200 |
---|---|---|
committer | Avi Kivity <avi@redhat.com> | 2011-11-28 15:38:45 +0200 |
commit | 9bac7d6c157f1e0dfa4dbf2c65ec994eb1a4a3a2 (patch) | |
tree | e9d7abd04a119587dcea23e4d5239dd32bbf3127 | |
parent | 750ecd444ff7e4e27928d65164228b3e1ae5a95b (diff) |
omap2: convert to memory API (part I)
Signed-off-by: Avi Kivity <avi@redhat.com>
-rw-r--r-- | hw/omap2.c | 103 |
1 files changed, 55 insertions, 48 deletions
diff --git a/hw/omap2.c b/hw/omap2.c index 3a7b210696..a5f9b7d4e4 100644 --- a/hw/omap2.c +++ b/hw/omap2.c @@ -33,6 +33,7 @@ /* Enhanced Audio Controller (CODEC only) */ struct omap_eac_s { qemu_irq irq; + MemoryRegion iomem; uint16_t sysconfig; uint8_t config[4]; @@ -323,11 +324,16 @@ static void omap_eac_reset(struct omap_eac_s *s) omap_eac_interrupt_update(s); } -static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr) +static uint64_t omap_eac_read(void *opaque, target_phys_addr_t addr, + unsigned size) { struct omap_eac_s *s = (struct omap_eac_s *) opaque; uint32_t ret; + if (size != 2) { + return omap_badwidth_read16(opaque, addr); + } + switch (addr) { case 0x000: /* CPCFR1 */ return s->config[0]; @@ -435,10 +441,14 @@ static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr) } static void omap_eac_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value, unsigned size) { struct omap_eac_s *s = (struct omap_eac_s *) opaque; + if (size != 2) { + return omap_badwidth_write16(opaque, addr, value); + } + switch (addr) { case 0x098: /* APD1LCR */ case 0x09c: /* APD1RCR */ @@ -574,22 +584,15 @@ static void omap_eac_write(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const omap_eac_readfn[] = { - omap_badwidth_read16, - omap_eac_read, - omap_badwidth_read16, -}; - -static CPUWriteMemoryFunc * const omap_eac_writefn[] = { - omap_badwidth_write16, - omap_eac_write, - omap_badwidth_write16, +static const MemoryRegionOps omap_eac_ops = { + .read = omap_eac_read, + .write = omap_eac_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta, qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk) { - int iomemtype; struct omap_eac_s *s = (struct omap_eac_s *) g_malloc0(sizeof(struct omap_eac_s)); @@ -600,9 +603,9 @@ static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta, AUD_register_card("OMAP EAC", &s->codec.card); - iomemtype = cpu_register_io_memory(omap_eac_readfn, - omap_eac_writefn, s, DEVICE_NATIVE_ENDIAN); - omap_l4_attach(ta, 0, iomemtype); + memory_region_init_io(&s->iomem, &omap_eac_ops, s, "omap.eac", + omap_l4_region_size(ta, 0)); + omap_l4_attach_region(ta, 0, &s->iomem); return s; } @@ -610,6 +613,8 @@ static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta, /* STI/XTI (emulation interface) console - reverse engineered only */ struct omap_sti_s { qemu_irq irq; + MemoryRegion iomem; + MemoryRegion iomem_fifo; CharDriverState *chr; uint32_t sysconfig; @@ -639,10 +644,15 @@ static void omap_sti_reset(struct omap_sti_s *s) omap_sti_interrupt_update(s); } -static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr) +static uint64_t omap_sti_read(void *opaque, target_phys_addr_t addr, + unsigned size) { struct omap_sti_s *s = (struct omap_sti_s *) opaque; + if (size != 4) { + return omap_badwidth_read32(opaque, addr); + } + switch (addr) { case 0x00: /* STI_REVISION */ return 0x10; @@ -676,10 +686,14 @@ static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr) } static void omap_sti_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value, unsigned size) { struct omap_sti_s *s = (struct omap_sti_s *) opaque; + if (size != 4) { + return omap_badwidth_write32(opaque, addr, value); + } + switch (addr) { case 0x00: /* STI_REVISION */ case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */ @@ -721,31 +735,30 @@ static void omap_sti_write(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const omap_sti_readfn[] = { - omap_badwidth_read32, - omap_badwidth_read32, - omap_sti_read, +static const MemoryRegionOps omap_sti_ops = { + .read = omap_sti_read, + .write = omap_sti_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; -static CPUWriteMemoryFunc * const omap_sti_writefn[] = { - omap_badwidth_write32, - omap_badwidth_write32, - omap_sti_write, -}; - -static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr) +static uint64_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr, + unsigned size) { OMAP_BAD_REG(addr); return 0; } static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr, - uint32_t value) + uint64_t value, unsigned size) { struct omap_sti_s *s = (struct omap_sti_s *) opaque; int ch = addr >> 6; uint8_t byte = value; + if (size != 1) { + return omap_badwidth_write8(opaque, addr, size); + } + if (ch == STI_TRACE_CONTROL_CHANNEL) { /* Flush channel <i>value</i>. */ qemu_chr_fe_write(s->chr, (const uint8_t *) "\r", 1); @@ -759,23 +772,17 @@ static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr, } } -static CPUReadMemoryFunc * const omap_sti_fifo_readfn[] = { - omap_sti_fifo_read, - omap_badwidth_read8, - omap_badwidth_read8, -}; - -static CPUWriteMemoryFunc * const omap_sti_fifo_writefn[] = { - omap_sti_fifo_write, - omap_badwidth_write8, - omap_badwidth_write8, +static const MemoryRegionOps omap_sti_fifo_ops = { + .read = omap_sti_fifo_read, + .write = omap_sti_fifo_write, + .endianness = DEVICE_NATIVE_ENDIAN, }; static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta, + MemoryRegion *sysmem, target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk, CharDriverState *chr) { - int iomemtype; struct omap_sti_s *s = (struct omap_sti_s *) g_malloc0(sizeof(struct omap_sti_s)); @@ -784,13 +791,13 @@ static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta, s->chr = chr ?: qemu_chr_new("null", "null", NULL); - iomemtype = cpu_register_io_memory(omap_sti_readfn, - omap_sti_writefn, s, DEVICE_NATIVE_ENDIAN); - omap_l4_attach(ta, 0, iomemtype); + memory_region_init_io(&s->iomem, &omap_sti_ops, s, "omap.sti", + omap_l4_region_size(ta, 0)); + omap_l4_attach_region(ta, 0, &s->iomem); - iomemtype = cpu_register_io_memory(omap_sti_fifo_readfn, - omap_sti_fifo_writefn, s, DEVICE_NATIVE_ENDIAN); - cpu_register_physical_memory(channel_base, 0x10000, iomemtype); + memory_region_init_io(&s->iomem_fifo, &omap_sti_fifo_ops, s, + "omap.sti.fifo", 0x10000); + memory_region_add_subregion(sysmem, channel_base, &s->iomem_fifo); return s; } @@ -2457,7 +2464,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, omap_findclk(s, "dss_l3_iclk"), omap_findclk(s, "dss_l4_iclk")); - omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000, + omap_sti_init(omap_l4ta(s->l4, 18), sysmem, 0x54000000, qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_STI), omap_findclk(s, "emul_ck"), serial_hds[0] && serial_hds[1] && serial_hds[2] ? |