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| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-08 15:51:32 +0000 |
|---|---|---|
| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-07-08 15:51:32 +0000 |
| commit | f7350b47dab4b2c84b67fa8cc003494b3ef7a032 (patch) | |
| tree | 1dcee1db8b93ecf6e6d9ac2baa3160b2bbffe6ee | |
| parent | b115bb3febe985bbc81d4dcfd82966fe94c54277 (diff) | |
Implement some Ultrasparc cache ASIs used by SILO
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4858 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | target-sparc/op_helper.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index f15cc224be..54db5f4e4f 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -1687,6 +1687,16 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) } break; } + case 0x46: // D-cache data + case 0x47: // D-cache tag access + case 0x4e: // E-cache tag data + case 0x66: // I-cache instruction access + case 0x67: // I-cache tag access + case 0x6e: // I-cache predecode + case 0x6f: // I-cache LRU etc. + case 0x76: // E-cache tag + case 0x7e: // E-cache tag + break; case 0x59: // D-MMU 8k TSB pointer case 0x5a: // D-MMU 64k TSB pointer case 0x5b: // D-MMU data pointer @@ -2040,6 +2050,16 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) case 0x49: // Interrupt data receive // XXX return; + case 0x46: // D-cache data + case 0x47: // D-cache tag access + case 0x4e: // E-cache tag data + case 0x66: // I-cache instruction access + case 0x67: // I-cache tag access + case 0x6e: // I-cache predecode + case 0x6f: // I-cache LRU etc. + case 0x76: // E-cache tag + case 0x7e: // E-cache tag + return; case 0x51: // I-MMU 8k TSB pointer, RO case 0x52: // I-MMU 64k TSB pointer, RO case 0x56: // I-MMU tag read, RO |