diff options
| author | Tsuneo Saito <tsnsaito@gmail.com> | 2011-07-14 18:41:38 +0900 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2011-07-14 15:36:10 +0000 |
| commit | e1ef36c4a34082a075182ec0ba44c80a2dbf43c2 (patch) | |
| tree | bad6e2ee78a026af67f82fb708f93b2015c00d19 | |
| parent | 8872eb4f567b9ae36dbd9c320f6a86c53a776d43 (diff) | |
SPARC64: Implement stfa/stdfa/stqfa instrcutions properly
This patch implements sparcv9 stfa/stdfa/stqfa instructions
with non block-store ASIs.
Signed-off-by: Tsuneo Saito <tsnsaito@gmail.com>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
| -rw-r--r-- | target-sparc/op_helper.c | 15 | ||||
| -rw-r--r-- | target-sparc/translate.c | 2 |
2 files changed, 11 insertions, 6 deletions
diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index a75ac4f3d0..fe71829ecc 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -3396,6 +3396,7 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd) { unsigned int i; target_ulong val = 0; + CPU_DoubleU u; helper_check_align(addr, 3); addr = asi_address_mask(env, asi, addr); @@ -3440,16 +3441,22 @@ void helper_stf_asi(target_ulong addr, int asi, int size, int rd) switch(size) { default: case 4: - val = *((uint32_t *)&env->fpr[rd]); + helper_st_asi(addr, *(uint32_t *)&env->fpr[rd], asi, size); break; case 8: - val = *((int64_t *)&DT0); + u.l.upper = *(uint32_t *)&env->fpr[rd++]; + u.l.lower = *(uint32_t *)&env->fpr[rd++]; + helper_st_asi(addr, u.ll, asi, size); break; case 16: - // XXX + u.l.upper = *(uint32_t *)&env->fpr[rd++]; + u.l.lower = *(uint32_t *)&env->fpr[rd++]; + helper_st_asi(addr, u.ll, asi, 8); + u.l.upper = *(uint32_t *)&env->fpr[rd++]; + u.l.lower = *(uint32_t *)&env->fpr[rd++]; + helper_st_asi(addr + 8, u.ll, asi, 8); break; } - helper_st_asi(addr, val, asi, size); } target_ulong helper_cas_asi(target_ulong addr, target_ulong val1, diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 1e7e68d397..a5a8eaf308 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -4742,12 +4742,10 @@ static void disas_sparc_insn(DisasContext * dc) r_const = tcg_const_i32(7); gen_helper_check_align(cpu_addr, r_const); tcg_temp_free_i32(r_const); - gen_op_load_fpr_QT0(QFPREG(rd)); gen_stf_asi(cpu_addr, insn, 16, QFPREG(rd)); } break; case 0x37: /* V9 stdfa */ - gen_op_load_fpr_DT0(DFPREG(rd)); gen_stf_asi(cpu_addr, insn, 8, DFPREG(rd)); break; case 0x3c: /* V9 casa */ |