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authorths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2007-04-28 20:45:04 +0000
committerths <ths@c046a42c-6fe2-441c-8c8c-71466251a162>2007-04-28 20:45:04 +0000
commit7faa239ca39b986a64ca99056311b32bc6cff55f (patch)
treef1715c16527b9c064e86049597e078be4d9999c6
parent85a6f129250efde1fe0af91a981d5006a0646b96 (diff)
Fix length mismatch condition, by Wang Cheng Yeh.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2735 c046a42c-6fe2-441c-8c8c-71466251a162
-rw-r--r--hw/lsi53c895a.c5
1 files changed, 3 insertions, 2 deletions
diff --git a/hw/lsi53c895a.c b/hw/lsi53c895a.c
index 71afd1f739..19bf2a195c 100644
--- a/hw/lsi53c895a.c
+++ b/hw/lsi53c895a.c
@@ -855,6 +855,7 @@ again:
offset = sxt24(addr);
cpu_physical_memory_read(s->dsa + offset, (uint8_t *)buf, 8);
s->dbc = cpu_to_le32(buf[0]);
+ s->rbc = s->dbc;
addr = cpu_to_le32(buf[1]);
}
if ((s->sstat1 & PHASE_MASK) != ((insn >> 24) & 7)) {
@@ -864,6 +865,8 @@ again:
break;
}
s->dnad = addr;
+ /* ??? Set ESA. */
+ s->ia = s->dsp - 8;
switch (s->sstat1 & 0x7) {
case PHASE_DO:
s->waiting = 2;
@@ -898,8 +901,6 @@ again:
s->sbc = s->dbc;
s->rbc -= s->dbc;
s->ua = addr + s->dbc;
- /* ??? Set ESA. */
- s->ia = s->dsp - 8;
break;
case 1: /* IO or Read/Write instruction. */