diff options
| author | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2017-06-20 13:13:26 +0200 |
|---|---|---|
| committer | Edgar E. Iglesias <edgar.iglesias@xilinx.com> | 2017-07-04 09:22:20 +0200 |
| commit | 5683750909fb407261b5ad00fed4ad9460ab6845 (patch) | |
| tree | 5bd8ed33539988cc54bfe2c48dde46de3120812b | |
| parent | 9b9643181a2324f4ecefd39367fd83be2ba837d6 (diff) | |
target-microblaze: Introduce a use-msr-instr property
Introduce a use-msr-instr property making msr instructions
optional.
Reviewed-by: Alistair Francis <alistair.francis@xilinx.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
| -rw-r--r-- | target/microblaze/cpu.c | 5 | ||||
| -rw-r--r-- | target/microblaze/cpu.h | 1 | ||||
| -rw-r--r-- | target/microblaze/translate.c | 2 |
3 files changed, 5 insertions, 3 deletions
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 70e47437f0..bc965055ab 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -157,7 +157,6 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) | PVR2_D_LMB_MASK \ | PVR2_I_OPB_MASK \ | PVR2_I_LMB_MASK \ - | PVR2_USE_MSR_INSTR \ | PVR2_USE_PCMP_INSTR \ | PVR2_FPU_EXC_MASK \ | 0; @@ -188,7 +187,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | (cpu->cfg.use_hw_mul > 1 ? PVR2_USE_MUL64_MASK : 0) | (cpu->cfg.use_barrel ? PVR2_USE_BARREL_MASK : 0) | - (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0); + (cpu->cfg.use_div ? PVR2_USE_DIV_MASK : 0) | + (cpu->cfg.use_msr_instr ? PVR2_USE_MSR_INSTR : 0); env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; @@ -241,6 +241,7 @@ static Property mb_properties[] = { DEFINE_PROP_UINT8("use-hw-mul", MicroBlazeCPU, cfg.use_hw_mul, 2), DEFINE_PROP_BOOL("use-barrel", MicroBlazeCPU, cfg.use_barrel, true), DEFINE_PROP_BOOL("use-div", MicroBlazeCPU, cfg.use_div, true), + DEFINE_PROP_BOOL("use-msr-instr", MicroBlazeCPU, cfg.use_msr_instr, true), DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true), DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback, false), diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e202229c08..5c960d01d3 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -301,6 +301,7 @@ struct MicroBlazeCPU { uint8_t use_hw_mul; bool use_barrel; bool use_div; + bool use_msr_instr; bool use_mmu; bool dcache_writeback; bool endi; diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 36caa037ec..bb1bdfa583 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -443,7 +443,7 @@ static void dec_msr(DisasContext *dc) LOG_DIS("msr%s r%d imm=%x\n", clr ? "clr" : "set", dc->rd, dc->imm); - if (!(dc->cpu->env.pvr.regs[2] & PVR2_USE_MSR_INSTR)) { + if (!dc->cpu->cfg.use_msr_instr) { /* nop??? */ return; } |