diff options
| author | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-12-10 22:08:10 +0000 |
|---|---|---|
| committer | ths <ths@c046a42c-6fe2-441c-8c8c-71466251a162> | 2006-12-10 22:08:10 +0000 |
| commit | ca7c2b1b9f984f622c7495004483016fee61e489 (patch) | |
| tree | 039162ed6c3010cb651694b5ccc850033fdf3a2d | |
| parent | 7d600c804d79e21254a20b953d6bd175597d752d (diff) | |
Handle invalid accesses as SIGILL for mips/mipsel userland emulation.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2235 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | linux-user/main.c | 2 | ||||
| -rw-r--r-- | target-mips/helper.c | 7 | ||||
| -rw-r--r-- | target-mips/translate.c | 3 |
3 files changed, 12 insertions, 0 deletions
diff --git a/linux-user/main.c b/linux-user/main.c index 6dd08022f0..c423d299b5 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -1352,6 +1352,8 @@ void cpu_loop(CPUMIPSState *env) } } break; + case EXCP_TLBL: + case EXCP_TLBS: case EXCP_CpU: case EXCP_RI: info.si_signo = TARGET_SIGILL; diff --git a/target-mips/helper.c b/target-mips/helper.c index a222d6b0ec..a0a56d8f04 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -243,6 +243,12 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw, return ret; } +#if defined(CONFIG_USER_ONLY) +void do_interrupt (CPUState *env) +{ + env->exception_index = EXCP_NONE; +} +#else void do_interrupt (CPUState *env) { target_ulong offset; @@ -409,3 +415,4 @@ void do_interrupt (CPUState *env) } env->exception_index = EXCP_NONE; } +#endif /* !defined(CONFIG_USER_ONLY) */ diff --git a/target-mips/translate.c b/target-mips/translate.c index 74fa114160..64f7d75650 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -4072,6 +4072,7 @@ void cpu_reset (CPUMIPSState *env) tlb_flush(env, 1); /* Minimal init */ +#if !defined(CONFIG_USER_ONLY) if (env->hflags & MIPS_HFLAG_BMASK) { /* If the exception was raised from a delay slot, * come back to the jump. */ @@ -4098,9 +4099,11 @@ void cpu_reset (CPUMIPSState *env) /* Count register increments in debug mode, EJTAG version 1 */ env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER); env->CP0_PRid = MIPS_CPU; +#endif env->exception_index = EXCP_NONE; #if defined(CONFIG_USER_ONLY) env->hflags |= MIPS_HFLAG_UM; + env->user_mode_only = 1; #endif #ifdef MIPS_USES_FPU env->fcr0 = MIPS_FCR0; |