diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2012-10-17 01:28:35 +0200 |
|---|---|---|
| committer | Blue Swirl <blauwirbel@gmail.com> | 2012-10-20 09:02:38 +0000 |
| commit | e7c8afb9058f9d46a089a9fb75cccf996886249c (patch) | |
| tree | 181c9dcbe5e7bb1bc350e8aadf4ba14e48718385 | |
| parent | a5089c050138933631b8755a664cfd275763b223 (diff) | |
target-sparc: fix FMOVr instruction
Like the MOVr instruction, the FMOVr instruction has the condition
encoded between bits 10 and 12.
Cc: Blue Swirl <blauwirbel@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
| -rw-r--r-- | target-sparc/translate.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 5df287629e..4321393688 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -3176,7 +3176,7 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) #define FMOVR(sz) \ do { \ DisasCompare cmp; \ - cond = GET_FIELD_SP(insn, 14, 17); \ + cond = GET_FIELD_SP(insn, 10, 12); \ cpu_src1 = get_src1(dc, insn); \ gen_compare_reg(&cmp, cond, cpu_src1); \ gen_fmov##sz(dc, &cmp, rd, rs2); \ |