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| author | Artyom Tarasenko <atar4qemu@gmail.com> | 2016-03-02 14:45:19 +0100 |
|---|---|---|
| committer | Artyom Tarasenko <atar4qemu@gmail.com> | 2017-01-18 22:03:44 +0100 |
| commit | b8e31b3cc6315bc5c6ec686c363c088c4fb1d0ea (patch) | |
| tree | 37c0cad1c03e5f4a065f1d0db9c37564004cd782 | |
| parent | 4ec3e34654990868ad73a5a452a46d7f9f9dd378 (diff) | |
target-sparc: implement UltraSPARC-T1 Strand status ASR
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
| -rw-r--r-- | target/sparc/translate.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/target/sparc/translate.c b/target/sparc/translate.c index 729f4e27ee..8902e44ca2 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -3429,6 +3429,17 @@ static void disas_sparc_insn(DisasContext * dc, unsigned int insn) case 0x19: /* System tick compare */ gen_store_gpr(dc, rd, cpu_stick_cmpr); break; + case 0x1a: /* UltraSPARC-T1 Strand status */ + /* XXX HYPV check maybe not enough, UA2005 & UA2007 describe + * this ASR as impl. dep + */ + CHECK_IU_FEATURE(dc, HYPV); + { + TCGv t = gen_dest_gpr(dc, rd); + tcg_gen_movi_tl(t, 1UL); + gen_store_gpr(dc, rd, t); + } + break; case 0x10: /* Performance Control */ case 0x11: /* Performance Instrumentation Counter */ case 0x12: /* Dispatch Control */ |