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authorPeter Maydell <peter.maydell@linaro.org>2015-05-29 11:28:53 +0100
committerPeter Maydell <peter.maydell@linaro.org>2015-05-29 11:28:53 +0100
commit647f767ba3b37fb229275086187e96242248a4ac (patch)
treed12006674cf5dd9ac291ac0d7582a967e5313c1c
parent9dbbc748d671c70599101836cd1c2719d92f3017 (diff)
target-arm: Move TB flags down to fill gap
Deleting the now-unused ARM_TBFLAG_CPACR_FPEN left a gap in the bit usage; move the following ARM_TBFLAG_XSCALE_CPAR and ARM_TBFLAG_NS_SHIFT down 3 bits to fill the gap. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
-rw-r--r--target-arm/cpu.h4
1 files changed, 2 insertions, 2 deletions
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index bf37c49739..21b5b8e538 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -1761,13 +1761,13 @@ static inline bool arm_singlestep_active(CPUARMState *env)
/* We store the bottom two bits of the CPAR as TB flags and handle
* checks on the other bits at runtime
*/
-#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 20
+#define ARM_TBFLAG_XSCALE_CPAR_SHIFT 17
#define ARM_TBFLAG_XSCALE_CPAR_MASK (3 << ARM_TBFLAG_XSCALE_CPAR_SHIFT)
/* Indicates whether cp register reads and writes by guest code should access
* the secure or nonsecure bank of banked registers; note that this is not
* the same thing as the current security state of the processor!
*/
-#define ARM_TBFLAG_NS_SHIFT 22
+#define ARM_TBFLAG_NS_SHIFT 19
#define ARM_TBFLAG_NS_MASK (1 << ARM_TBFLAG_NS_SHIFT)
/* Bit usage when in AArch64 state: currently we have no A64 specific bits */