diff options
| author | Richard Henderson <rth@twiddle.net> | 2013-06-04 11:37:17 -0700 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2013-11-30 07:45:13 +1300 |
| commit | cd629de1cf013e9654c6f0b92b2329f04dfaf880 (patch) | |
| tree | 32d1754eb99e7eeddc832ef2188c71afe492a6fd | |
| parent | b6a3e690b4f396633c75e18a9c3e7b6771fb71ba (diff) | |
tcg-ppc64: Use qemu_getauxval
Allow host detection on linux systems without glibc 2.16 or later.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <rth@twiddle.net>
| -rw-r--r-- | include/elf.h | 34 | ||||
| -rw-r--r-- | tcg/ppc64/tcg-target.c | 11 |
2 files changed, 36 insertions, 9 deletions
diff --git a/include/elf.h b/include/elf.h index b818091c7b..b68fc60458 100644 --- a/include/elf.h +++ b/include/elf.h @@ -411,6 +411,40 @@ typedef struct { #define R_SPARC_5 44 #define R_SPARC_6 45 +/* Bits present in AT_HWCAP for PowerPC. */ + +#define PPC_FEATURE_32 0x80000000 +#define PPC_FEATURE_64 0x40000000 +#define PPC_FEATURE_601_INSTR 0x20000000 +#define PPC_FEATURE_HAS_ALTIVEC 0x10000000 +#define PPC_FEATURE_HAS_FPU 0x08000000 +#define PPC_FEATURE_HAS_MMU 0x04000000 +#define PPC_FEATURE_HAS_4xxMAC 0x02000000 +#define PPC_FEATURE_UNIFIED_CACHE 0x01000000 +#define PPC_FEATURE_HAS_SPE 0x00800000 +#define PPC_FEATURE_HAS_EFP_SINGLE 0x00400000 +#define PPC_FEATURE_HAS_EFP_DOUBLE 0x00200000 +#define PPC_FEATURE_NO_TB 0x00100000 +#define PPC_FEATURE_POWER4 0x00080000 +#define PPC_FEATURE_POWER5 0x00040000 +#define PPC_FEATURE_POWER5_PLUS 0x00020000 +#define PPC_FEATURE_CELL 0x00010000 +#define PPC_FEATURE_BOOKE 0x00008000 +#define PPC_FEATURE_SMT 0x00004000 +#define PPC_FEATURE_ICACHE_SNOOP 0x00002000 +#define PPC_FEATURE_ARCH_2_05 0x00001000 +#define PPC_FEATURE_PA6T 0x00000800 +#define PPC_FEATURE_HAS_DFP 0x00000400 +#define PPC_FEATURE_POWER6_EXT 0x00000200 +#define PPC_FEATURE_ARCH_2_06 0x00000100 +#define PPC_FEATURE_HAS_VSX 0x00000080 + +#define PPC_FEATURE_PSERIES_PERFMON_COMPAT \ + 0x00000040 + +#define PPC_FEATURE_TRUE_LE 0x00000002 +#define PPC_FEATURE_PPC_LE 0x00000001 + /* Bits present in AT_HWCAP, primarily for Sparc32. */ #define HWCAP_SPARC_FLUSH 1 /* CPU supports flush instruction. */ diff --git a/tcg/ppc64/tcg-target.c b/tcg/ppc64/tcg-target.c index 6109d862db..06e440f9bc 100644 --- a/tcg/ppc64/tcg-target.c +++ b/tcg/ppc64/tcg-target.c @@ -45,15 +45,10 @@ static uint8_t *tb_ret_addr; #define GUEST_BASE 0 #endif -#ifdef CONFIG_GETAUXVAL -#include <sys/auxv.h> +#include "elf.h" static bool have_isa_2_06; #define HAVE_ISA_2_06 have_isa_2_06 #define HAVE_ISEL have_isa_2_06 -#else -#define HAVE_ISA_2_06 0 -#define HAVE_ISEL 0 -#endif #ifdef CONFIG_USE_GUEST_BASE #define TCG_GUEST_BASE_REG 30 @@ -2132,12 +2127,10 @@ static const TCGTargetOpDef ppc_op_defs[] = { static void tcg_target_init(TCGContext *s) { -#ifdef CONFIG_GETAUXVAL - unsigned long hwcap = getauxval(AT_HWCAP); + unsigned long hwcap = qemu_getauxval(AT_HWCAP); if (hwcap & PPC_FEATURE_ARCH_2_06) { have_isa_2_06 = true; } -#endif tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffffffff); tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffffffff); |