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authorPeter Maydell <peter.maydell@linaro.org>2012-10-18 14:11:42 +0100
committerBlue Swirl <blauwirbel@gmail.com>2012-10-20 07:56:22 +0000
commita5089c050138933631b8755a664cfd275763b223 (patch)
tree1a7003581b91e48854baf6af1c89c7ac3483e7b1
parentaf83c32bd44b6594db301b4ac8cb44e5eb85d4bf (diff)
hw/pl031: Use LOG_GUEST_ERROR
Use LOG_GUEST_ERROR rather than hw_error or direct fprintf. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
-rw-r--r--hw/pl031.c16
1 files changed, 10 insertions, 6 deletions
diff --git a/hw/pl031.c b/hw/pl031.c
index 9602664da6..6cbaf2386f 100644
--- a/hw/pl031.c
+++ b/hw/pl031.c
@@ -120,11 +120,13 @@ static uint64_t pl031_read(void *opaque, target_phys_addr_t offset,
case RTC_MIS:
return s->is & s->im;
case RTC_ICR:
- fprintf(stderr, "qemu: pl031_read: Unexpected offset 0x%x\n",
- (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pl031: read of write-only register at offset 0x%x\n",
+ (int)offset);
break;
default:
- hw_error("pl031_read: Bad offset 0x%x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pl031_read: Bad offset 0x%x\n", (int)offset);
break;
}
@@ -167,12 +169,14 @@ static void pl031_write(void * opaque, target_phys_addr_t offset,
case RTC_DR:
case RTC_MIS:
case RTC_RIS:
- fprintf(stderr, "qemu: pl031_write: Unexpected offset 0x%x\n",
- (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pl031: write to read-only register at offset 0x%x\n",
+ (int)offset);
break;
default:
- hw_error("pl031_write: Bad offset 0x%x\n", (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pl031_write: Bad offset 0x%x\n", (int)offset);
break;
}
}