diff options
| author | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-01-04 22:51:59 +0000 |
|---|---|---|
| committer | aurel32 <aurel32@c046a42c-6fe2-441c-8c8c-71466251a162> | 2009-01-04 22:51:59 +0000 |
| commit | 785f451b62c8008428343d84549d175cd4f9d099 (patch) | |
| tree | 25ef803d7c52889640f4fedfb7edcb2bab99dcc2 | |
| parent | 8142cddda25b8010c0fe2d6bb3aa562a2048b347 (diff) | |
target-ppc: Add m{f,t}vscr instructions.
Based on a patch by Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6190 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | target-ppc/translate.c | 27 |
1 files changed, 27 insertions, 0 deletions
diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 1dcc5813ac..03dac58e76 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -6228,6 +6228,33 @@ GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC) tcg_temp_free_ptr(rd); } +GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC) +{ + TCGv_i32 t; + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0); + t = tcg_temp_new_i32(); + tcg_gen_ld_i32(t, cpu_env, offsetof(CPUState, vscr)); + tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t); + tcg_temp_free(t); +} + +GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC) +{ + TCGv_i32 t; + if (unlikely(!ctx->altivec_enabled)) { + gen_exception(ctx, POWERPC_EXCP_VPU); + return; + } + t = tcg_temp_new_i32(); + tcg_gen_trunc_i64_i32(t, cpu_avrl[rD(ctx->opcode)]); + tcg_gen_st_i32(t, cpu_env, offsetof(CPUState, vscr)); + tcg_temp_free_i32(t); +} + /* Logical operations */ #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \ GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC) \ |