diff options
| author | Evgeny Voevodin <e.voevodin@samsung.com> | 2012-04-13 11:39:06 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2012-04-13 11:39:06 +0000 |
| commit | 3f088e36de5a72a69e530d4bbf1fabaa507da0db (patch) | |
| tree | 29971aefa7c2fec7ca7fe1571b885d52d1721a05 | |
| parent | b85f62d7811c80646065f8f96c2248ea86cfd911 (diff) | |
ARM: Exynos4210: Drop gic_cpu_write() after initialization.
Remove gic_cpu_write() call after initialization that was emulating
functionality of earliest SOC bootloader which enables external
GIC CPU1 interface. Instead introduce Exynos4210-specific secondary
CPU bootloader, which enables both Internal and External GIC CPU1
interfaces.
Signed-off-by: Evgeny Voevodin <e.voevodin@samsung.com>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | hw/exynos4210.c | 30 | ||||
| -rw-r--r-- | hw/exynos4210.h | 3 | ||||
| -rw-r--r-- | hw/exynos4210_gic.c | 2 | ||||
| -rw-r--r-- | hw/exynos4_boards.c | 1 |
4 files changed, 34 insertions, 2 deletions
diff --git a/hw/exynos4210.c b/hw/exynos4210.c index f904370505..afc4bdc7e0 100644 --- a/hw/exynos4210.c +++ b/hw/exynos4210.c @@ -25,6 +25,7 @@ #include "sysemu.h" #include "sysbus.h" #include "arm-misc.h" +#include "loader.h" #include "exynos4210.h" #define EXYNOS4210_CHIPID_ADDR 0x10000000 @@ -64,6 +65,35 @@ static uint8_t chipid_and_omr[] = { 0x11, 0x02, 0x21, 0x43, 0x09, 0x00, 0x00, 0x00 }; +void exynos4210_write_secondary(CPUARMState *env, + const struct arm_boot_info *info) +{ + int n; + uint32_t smpboot[] = { + 0xe59f3024, /* ldr r3, External gic_cpu_if */ + 0xe59f2024, /* ldr r2, Internal gic_cpu_if */ + 0xe59f0024, /* ldr r0, startaddr */ + 0xe3a01001, /* mov r1, #1 */ + 0xe5821000, /* str r1, [r2] */ + 0xe5831000, /* str r1, [r3] */ + 0xe320f003, /* wfi */ + 0xe5901000, /* ldr r1, [r0] */ + 0xe1110001, /* tst r1, r1 */ + 0x0afffffb, /* beq <wfi> */ + 0xe12fff11, /* bx r1 */ + EXYNOS4210_EXT_GIC_CPU_BASE_ADDR, + 0, /* gic_cpu_if: base address of Internal GIC CPU interface */ + 0 /* bootreg: Boot register address is held here */ + }; + smpboot[ARRAY_SIZE(smpboot) - 1] = info->smp_bootreg_addr; + smpboot[ARRAY_SIZE(smpboot) - 2] = info->gic_cpu_if_addr; + for (n = 0; n < ARRAY_SIZE(smpboot); n++) { + smpboot[n] = tswap32(smpboot[n]); + } + rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), + info->smp_loader_start); +} + Exynos4210State *exynos4210_init(MemoryRegion *system_mem, unsigned long ram_size) { diff --git a/hw/exynos4210.h b/hw/exynos4210.h index c112e03bfb..f7c7027302 100644 --- a/hw/exynos4210.h +++ b/hw/exynos4210.h @@ -97,6 +97,9 @@ typedef struct Exynos4210State { MemoryRegion bootreg_mem; } Exynos4210State; +void exynos4210_write_secondary(CPUARMState *env, + const struct arm_boot_info *info); + Exynos4210State *exynos4210_init(MemoryRegion *system_mem, unsigned long ram_size); diff --git a/hw/exynos4210_gic.c b/hw/exynos4210_gic.c index ec13140f9f..3ba9063f3c 100644 --- a/hw/exynos4210_gic.c +++ b/hw/exynos4210_gic.c @@ -321,8 +321,6 @@ static int exynos4210_gic_init(SysBusDevice *dev) sysbus_init_mmio(dev, &s->cpu_container); sysbus_init_mmio(dev, &s->dist_container); - gic_cpu_write(&s->gic, 1, 0, 1); - return 0; } diff --git a/hw/exynos4_boards.c b/hw/exynos4_boards.c index 553a02b910..ea32c51dcc 100644 --- a/hw/exynos4_boards.c +++ b/hw/exynos4_boards.c @@ -70,6 +70,7 @@ static struct arm_boot_info exynos4_board_binfo = { .loader_start = EXYNOS4210_BASE_BOOT_ADDR, .smp_loader_start = EXYNOS4210_SMP_BOOT_ADDR, .nb_cpus = EXYNOS4210_NCPUS, + .write_secondary_boot = exynos4210_write_secondary, }; static QEMUMachine exynos4_machines[EXYNOS4_NUM_OF_BOARDS]; |