diff options
| author | Alex Zuepke <alexander.zuepke@hs-rm.de> | 2014-12-12 15:10:29 +0100 |
|---|---|---|
| committer | Bastian Koppelmann <kbastian@mail.uni-paderborn.de> | 2014-12-21 18:32:27 +0000 |
| commit | 4b5b44357651b7563790e246be64bc55f4d90d47 (patch) | |
| tree | 89850aea6e677e3536837527a84220a4e7140b76 | |
| parent | af715d980271a1c8ea9596bf9147b5421a49e01a (diff) | |
target-tricore: add missing 64-bit MOV in RLC format
Signed-off-by: Alex Zuepke <alexander.zuepke@hs-rm.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
| -rw-r--r-- | target-tricore/translate.c | 12 | ||||
| -rw-r--r-- | target-tricore/tricore-opcodes.h | 1 |
2 files changed, 13 insertions, 0 deletions
diff --git a/target-tricore/translate.c b/target-tricore/translate.c index c1322238a7..e3eeedba95 100644 --- a/target-tricore/translate.c +++ b/target-tricore/translate.c @@ -3781,6 +3781,17 @@ static void decode_rlc_opc(CPUTriCoreState *env, DisasContext *ctx, case OPC1_32_RLC_MOV: tcg_gen_movi_tl(cpu_gpr_d[r2], const16); break; + case OPC1_32_RLC_MOV_64: + if (tricore_feature(env, TRICORE_FEATURE_16)) { + if ((r2 & 0x1) != 0) { + /* TODO: raise OPD trap */ + } + tcg_gen_movi_tl(cpu_gpr_d[r2], const16); + tcg_gen_movi_tl(cpu_gpr_d[r2+1], const16 >> 15); + } else { + /* TODO: raise illegal opcode trap */ + } + break; case OPC1_32_RLC_MOV_U: const16 = MASK_OP_RLC_CONST16(ctx->opcode); tcg_gen_movi_tl(cpu_gpr_d[r2], const16); @@ -4021,6 +4032,7 @@ static void decode_32Bit_opc(CPUTriCoreState *env, DisasContext *ctx) case OPC1_32_RLC_ADDIH_A: case OPC1_32_RLC_MFCR: case OPC1_32_RLC_MOV: + case OPC1_32_RLC_MOV_64: case OPC1_32_RLC_MOV_U: case OPC1_32_RLC_MOV_H: case OPC1_32_RLC_MOVH_A: diff --git a/target-tricore/tricore-opcodes.h b/target-tricore/tricore-opcodes.h index 7aa6aed4d3..a76a7e4c45 100644 --- a/target-tricore/tricore-opcodes.h +++ b/target-tricore/tricore-opcodes.h @@ -487,6 +487,7 @@ enum { OPC1_32_RLC_ADDIH_A = 0x11, OPC1_32_RLC_MFCR = 0x4d, OPC1_32_RLC_MOV = 0x3b, + OPC1_32_RLC_MOV_64 = 0xfb, /* 1.6 only */ OPC1_32_RLC_MOV_U = 0xbb, OPC1_32_RLC_MOV_H = 0x7b, OPC1_32_RLC_MOVH_A = 0x91, |