diff options
| author | Tom Musta <tommusta@gmail.com> | 2014-05-29 09:12:24 -0500 |
|---|---|---|
| committer | Alexander Graf <agraf@suse.de> | 2014-06-16 13:24:40 +0200 |
| commit | 4b1daa72d3b68b050bb9013edd0888972a0e22dd (patch) | |
| tree | 52fc2bf24c522582b9002b0d478b1c70fb37e3b1 | |
| parent | f46e9a0b9911fcfbc13f85f3a8808067990a0f5c (diff) | |
target-ppc: Store Quadword Conditional Drops Size Bit
The size and register information are encoded into the reserve_info field
of CPU state in the store conditional translation code. Specifically, the
size is shifted left by 5 bits (see target-ppc/translate.c gen_conditional_store).
The user-mode store conditional code erroneously extracts the size by ANDing
with a 4 bit mask; this breaks if size >= 16.
Eliminate the mask to make the extraction of size mirror its encoding.
Signed-off-by: Tom Musta <tommusta@gmail.com>
Signed-off-by: Alexander Graf <agraf@suse.de>
| -rw-r--r-- | linux-user/main.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/linux-user/main.c b/linux-user/main.c index f577e19646..a87c6f7ed4 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -1497,7 +1497,7 @@ static int do_store_exclusive(CPUPPCState *env) segv = 1; } else { int reg = env->reserve_info & 0x1f; - int size = (env->reserve_info >> 5) & 0xf; + int size = env->reserve_info >> 5; int stored = 0; if (addr == env->reserve_addr) { |