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authorYang Zhong <yang.zhong@intel.com>2017-07-03 18:12:19 +0800
committerPaolo Bonzini <pbonzini@redhat.com>2017-07-05 09:12:44 +0200
commit1d8ad165b688759bbf00e40431ee9fde8817d190 (patch)
tree4f43b9fb62be94a50e57a94717d3ba9dd27a46af
parentdb573d2cf7ae6b5a4fc324be6f55e078fc218464 (diff)
target/i386: split cpu_set_mxcsr() and make cpu_set_fpuc() inline
Split the cpu_set_mxcsr() and make cpu_set_fpuc() inline with specific tcg code. Signed-off-by: Yang Zhong <yang.zhong@intel.com> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
-rw-r--r--target/i386/cpu.h21
-rw-r--r--target/i386/fpu_helper.c11
-rw-r--r--target/i386/machine.c5
3 files changed, 24 insertions, 13 deletions
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 8d9ba3686c..3495a91039 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1594,7 +1594,6 @@ void QEMU_NORETURN raise_interrupt(CPUX86State *nenv, int intno, int is_int,
/* cc_helper.c */
extern const uint8_t parity_table[256];
uint32_t cpu_cc_compute_all(CPUX86State *env1, int op);
-void update_fp_status(CPUX86State *env);
static inline uint32_t cpu_compute_eflags(CPUX86State *env)
{
@@ -1643,8 +1642,24 @@ static inline int32_t x86_get_a20_mask(CPUX86State *env)
}
/* fpu_helper.c */
-void cpu_set_mxcsr(CPUX86State *env, uint32_t val);
-void cpu_set_fpuc(CPUX86State *env, uint16_t val);
+void update_fp_status(CPUX86State *env);
+void update_mxcsr_status(CPUX86State *env);
+
+static inline void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
+{
+ env->mxcsr = mxcsr;
+ if (tcg_enabled()) {
+ update_mxcsr_status(env);
+ }
+}
+
+static inline void cpu_set_fpuc(CPUX86State *env, uint16_t fpuc)
+{
+ env->fpuc = fpuc;
+ if (tcg_enabled()) {
+ update_fp_status(env);
+ }
+}
/* mem_helper.c */
void helper_lock_init(void);
diff --git a/target/i386/fpu_helper.c b/target/i386/fpu_helper.c
index 34fb5fca66..9014b6f88a 100644
--- a/target/i386/fpu_helper.c
+++ b/target/i386/fpu_helper.c
@@ -1550,12 +1550,11 @@ void helper_xsetbv(CPUX86State *env, uint32_t ecx, uint64_t mask)
#define SSE_RC_CHOP 0x6000
#define SSE_FZ 0x8000
-void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
+void update_mxcsr_status(CPUX86State *env)
{
+ uint32_t mxcsr = env->mxcsr;
int rnd_type;
- env->mxcsr = mxcsr;
-
/* set rounding mode */
switch (mxcsr & SSE_RC_MASK) {
default:
@@ -1581,12 +1580,6 @@ void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
set_flush_to_zero((mxcsr & SSE_FZ) ? 1 : 0, &env->fp_status);
}
-void cpu_set_fpuc(CPUX86State *env, uint16_t val)
-{
- env->fpuc = val;
- update_fp_status(env);
-}
-
void helper_ldmxcsr(CPUX86State *env, uint32_t val)
{
cpu_set_mxcsr(env, val);
diff --git a/target/i386/machine.c b/target/i386/machine.c
index 53587ae88b..e0417fecaf 100644
--- a/target/i386/machine.c
+++ b/target/i386/machine.c
@@ -280,7 +280,10 @@ static int cpu_post_load(void *opaque, int version_id)
for(i = 0; i < 8; i++) {
env->fptags[i] = (env->fptag_vmstate >> i) & 1;
}
- update_fp_status(env);
+ if (tcg_enabled()) {
+ update_fp_status(env);
+ update_mxcsr_status(env);
+ }
cpu_breakpoint_remove_all(cs, BP_CPU);
cpu_watchpoint_remove_all(cs, BP_CPU);