diff options
| author | David Gibson <david@gibson.dropbear.id.au> | 2016-11-21 16:28:12 +1100 |
|---|---|---|
| committer | David Gibson <david@gibson.dropbear.id.au> | 2016-11-23 12:00:48 +1100 |
| commit | 16a2497bd44cac1856e259654fd304079bd1dcdc (patch) | |
| tree | 398ba68401a3398b67853e2bf37f6b808241ad4c | |
| parent | 39d97e14a151519c81955a0b82352b5596432f63 (diff) | |
target-ppc: Fix CPU migration from qemu-2.6 <-> later versions
When migration for target-ppc was converted to vmstate, several
VMSTATE_EQUAL() checks were foolishly included of things that really
should be internal state. Specifically we verified equality of the
insns_flags and insns_flags2 fields, which are used within TCG to
determine which groups of instructions are available on this cpu
model. Between qemu-2.6 and qemu-2.7 we made some changes to these
classes which broke migration.
This path fixes migration both forwards and backwards. On migration
from 2.6 to later versions we import the fields into teporary
variables, which we then ignore. In migration backwards, we populate
the temporary fields from the runtime fields, but mask out the bits
which were added after qemu-2.6, allowing the VMSTATE_EQUAL in
qemu-2.6 to accept the stream.
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Dr. David Alan Gilbert <dgilbert@redhat.com>
Reviewed-by: Thomas Huth <thuth@redhat.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
| -rw-r--r-- | target-ppc/cpu.h | 6 | ||||
| -rw-r--r-- | target-ppc/machine.c | 29 |
2 files changed, 31 insertions, 4 deletions
diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 1c90adb5d7..7798b2ec23 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1166,6 +1166,12 @@ struct PowerPCCPU { int cpu_dt_id; uint32_t max_compat; uint32_t cpu_version; + + /* fields used only during migration for compatibility hacks */ + target_ulong mig_msr_mask; + uint64_t mig_insns_flags; + uint64_t mig_insns_flags2; + uint32_t mig_nb_BATs; }; static inline PowerPCCPU *ppc_env_get_cpu(CPUPPCState *env) diff --git a/target-ppc/machine.c b/target-ppc/machine.c index e43cb6c39d..fcac263c7d 100644 --- a/target-ppc/machine.c +++ b/target-ppc/machine.c @@ -140,6 +140,21 @@ static void cpu_pre_save(void *opaque) PowerPCCPU *cpu = opaque; CPUPPCState *env = &cpu->env; int i; + uint64_t insns_compat_mask = + PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB + | PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES + | PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES + | PPC_FLOAT_STFIWX | PPC_FLOAT_EXT + | PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ + | PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC + | PPC_64B | PPC_64BX | PPC_ALTIVEC + | PPC_SEGMENT_64B | PPC_SLBI | PPC_POPCNTB | PPC_POPCNTWD; + uint64_t insns_compat_mask2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX + | PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 + | PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 + | PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 + | PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 + | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_TM; env->spr[SPR_LR] = env->lr; env->spr[SPR_CTR] = env->ctr; @@ -161,6 +176,12 @@ static void cpu_pre_save(void *opaque) env->spr[SPR_IBAT4U + 2*i] = env->IBAT[0][i+4]; env->spr[SPR_IBAT4U + 2*i + 1] = env->IBAT[1][i+4]; } + + /* Hacks for migration compatibility between 2.6, 2.7 & 2.8 */ + cpu->mig_msr_mask = env->msr_mask; + cpu->mig_insns_flags = env->insns_flags & insns_compat_mask; + cpu->mig_insns_flags2 = env->insns_flags2 & insns_compat_mask2; + cpu->mig_nb_BATs = env->nb_BATs; } static int cpu_post_load(void *opaque, int version_id) @@ -561,10 +582,10 @@ const VMStateDescription vmstate_ppc_cpu = { /* FIXME: access_type? */ /* Sanity checking */ - VMSTATE_UINTTL_EQUAL(env.msr_mask, PowerPCCPU), - VMSTATE_UINT64_EQUAL(env.insns_flags, PowerPCCPU), - VMSTATE_UINT64_EQUAL(env.insns_flags2, PowerPCCPU), - VMSTATE_UINT32_EQUAL(env.nb_BATs, PowerPCCPU), + VMSTATE_UINTTL(mig_msr_mask, PowerPCCPU), + VMSTATE_UINT64(mig_insns_flags, PowerPCCPU), + VMSTATE_UINT64(mig_insns_flags2, PowerPCCPU), + VMSTATE_UINT32(mig_nb_BATs, PowerPCCPU), VMSTATE_END_OF_LIST() }, .subsections = (const VMStateDescription*[]) { |