diff options
| author | Eduardo Habkost <ehabkost@redhat.com> | 2012-02-17 14:41:21 -0200 |
|---|---|---|
| committer | Anthony Liguori <aliguori@us.ibm.com> | 2012-02-22 13:24:28 -0600 |
| commit | 3ac8ebfe1c989e4a123d13fc0f1207fa4a9b37b5 (patch) | |
| tree | 83c64d0103fac6e9f65d587fe477cc74111d5ebd | |
| parent | f370be3c50c0aec7785e0f82c35a0e953f23dc5b (diff) | |
cpu defs: use Intel flag names for Intel models (v2)
Use 'i64' instead of 'lm' and 'xd' instead of 'nx' on Intel models.
The flags have different names on Intel docs, so use those names for clarity.
This is based on a previous patch from John Cooper where this was introduced
with many other changes at the same time. Original John's patch submission is
at Message-ID: <4DDAD5E7.2020002@redhat.com>, <http://marc.info/?l=qemu-devel&m=130618871926030>.
Changes v1 -> v2:
- Rebase patch against latest Qemu git tree
Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
| -rw-r--r-- | sysconfigs/target/target-x86_64.conf | 6 | ||||
| -rw-r--r-- | target-i386/cpuid.c | 4 |
2 files changed, 5 insertions, 5 deletions
diff --git a/sysconfigs/target/target-x86_64.conf b/sysconfigs/target/target-x86_64.conf index 67207787a9..09b255ebf5 100644 --- a/sysconfigs/target/target-x86_64.conf +++ b/sysconfigs/target/target-x86_64.conf @@ -9,7 +9,7 @@ stepping = "3" feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu" feature_ecx = "ssse3 sse3" - extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu" + extfeature_edx = "i64 fxsr mmx xd pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu" extfeature_ecx = "lahf_lm" xlevel = "0x8000000A" model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)" @@ -23,7 +23,7 @@ stepping = "3" feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu" feature_ecx = "sse4.1 cx16 ssse3 sse3" - extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu" + extfeature_edx = "i64 fxsr mmx xd pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu" extfeature_ecx = "lahf_lm" xlevel = "0x8000000A" model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)" @@ -37,7 +37,7 @@ stepping = "3" feature_edx = "sse2 sse fxsr mmx clflush pse36 pat cmov mca pge mtrr sep apic cx8 mce pae msr tsc pse de fpu" feature_ecx = "popcnt sse4.2 sse4.1 cx16 ssse3 sse3" - extfeature_edx = "lm fxsr mmx nx pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu" + extfeature_edx = "i64 fxsr mmx xd pat cmov pge syscall apic cx8 mce pae msr tsc pse de fpu" extfeature_ecx = "lahf_lm" xlevel = "0x8000000A" model_id = "Intel Core i7 9xx (Nehalem Class Core i7)" diff --git a/target-i386/cpuid.c b/target-i386/cpuid.c index aa19260a9e..ace2a6779c 100644 --- a/target-i386/cpuid.c +++ b/target-i386/cpuid.c @@ -59,9 +59,9 @@ static const char *ext2_feature_name[] = { "cx8" /* AMD CMPXCHG8B */, "apic", NULL, "syscall", "mtrr", "pge", "mca", "cmov", "pat", "pse36", NULL, NULL /* Linux mp */, - "nx" /* Intel xd */, NULL, "mmxext", "mmx", + "nx|xd", NULL, "mmxext", "mmx", "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp", - NULL, "lm" /* Intel 64 */, "3dnowext", "3dnow", + NULL, "lm|i64", "3dnowext", "3dnow", }; static const char *ext3_feature_name[] = { "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */, |