diff options
| author | Andreas Färber <afaerber@suse.de> | 2013-01-16 04:13:19 +0100 |
|---|---|---|
| committer | Andreas Färber <afaerber@suse.de> | 2013-02-16 14:50:57 +0100 |
| commit | b6e91ebfe06f1d90331d162259553a5330514143 (patch) | |
| tree | b03e3575a0b321943427f75a5728ba22acc9f506 | |
| parent | 55acb588dd184a1e33be0ff1fe23f8c19f88fd6c (diff) | |
target-sparc: Introduce QOM realizefn for SPARCCPU
Introduce realizefn and set realized = true in cpu_sparc_init().
Signed-off-by: Andreas Färber <afaerber@suse.de>
| -rw-r--r-- | target-sparc/cpu-qom.h | 2 | ||||
| -rw-r--r-- | target-sparc/cpu.c | 17 |
2 files changed, 18 insertions, 1 deletions
diff --git a/target-sparc/cpu-qom.h b/target-sparc/cpu-qom.h index 2a738ae360..89cd1cf2d3 100644 --- a/target-sparc/cpu-qom.h +++ b/target-sparc/cpu-qom.h @@ -38,6 +38,7 @@ /** * SPARCCPUClass: + * @parent_realize: The parent class' realize handler. * @parent_reset: The parent class' reset handler. * * A SPARC CPU model. @@ -47,6 +48,7 @@ typedef struct SPARCCPUClass { CPUClass parent_class; /*< public >*/ + DeviceRealize parent_realize; void (*parent_reset)(CPUState *cpu); } SPARCCPUClass; diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index 4bc1afc755..1690cf5b15 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -122,7 +122,8 @@ SPARCCPU *cpu_sparc_init(const char *cpu_model) object_unref(OBJECT(cpu)); return NULL; } - qemu_init_vcpu(env); + + object_property_set_bool(OBJECT(cpu), true, "realized", NULL); return cpu; } @@ -851,6 +852,16 @@ void cpu_dump_state(CPUSPARCState *env, FILE *f, fprintf_function cpu_fprintf, cpu_fprintf(f, "\n"); } +static void sparc_cpu_realizefn(DeviceState *dev, Error **errp) +{ + SPARCCPU *cpu = SPARC_CPU(dev); + SPARCCPUClass *scc = SPARC_CPU_GET_CLASS(dev); + + qemu_init_vcpu(&cpu->env); + + scc->parent_realize(dev, errp); +} + static void sparc_cpu_initfn(Object *obj) { SPARCCPU *cpu = SPARC_CPU(obj); @@ -871,6 +882,10 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) { SPARCCPUClass *scc = SPARC_CPU_CLASS(oc); CPUClass *cc = CPU_CLASS(oc); + DeviceClass *dc = DEVICE_CLASS(oc); + + scc->parent_realize = dc->realize; + dc->realize = sparc_cpu_realizefn; scc->parent_reset = cc->reset; cc->reset = sparc_cpu_reset; |