diff options
| author | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-07 14:18:02 +0000 |
|---|---|---|
| committer | balrog <balrog@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-07 14:18:02 +0000 |
| commit | 955a7dd5e857bdeb1d41893a5ac9c1e02c327382 (patch) | |
| tree | cf76895137766a409b71b7f70fab54e669714c3f | |
| parent | ded9d29547922ba1ade973d6031313411c98e214 (diff) | |
ARM: fix smmul and smmla/smmls usage of registers (Mans Rullgard).
This fixes the destination and accumulator registers for the smmul
and smmla instructions.
Signed-off-by: Mans Rullgard <mans@mansr.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5913 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | target-arm/translate.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 29ec0ed338..0650bc3a21 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -6507,8 +6507,8 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) tcg_gen_shri_i64(tmp64, tmp64, 32); tmp = new_tmp(); tcg_gen_trunc_i64_i32(tmp, tmp64); - if (rn != 15) { - tmp2 = load_reg(s, rn); + if (rd != 15) { + tmp2 = load_reg(s, rd); if (insn & (1 << 6)) { tcg_gen_sub_i32(tmp, tmp, tmp2); } else { @@ -6516,7 +6516,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s) } dead_tmp(tmp2); } - store_reg(s, rd, tmp); + store_reg(s, rn, tmp); } else { if (insn & (1 << 5)) gen_swap_half(tmp2); |