diff options
| author | Max Filippov <jcmvbkbc@gmail.com> | 2020-07-11 02:58:22 -0700 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2020-08-21 12:48:15 -0700 |
| commit | de6b55cbda2a26fb8889c8a8b44c139d7e106dce (patch) | |
| tree | 39226f6cfb491940e5f0b88fd1ff4f60bd6072e1 | |
| parent | 5dbb4c96d50c6ef74d4fd71a5a0fd9763d5a3662 (diff) | |
target/xtensa: add DFPU option
Double precision floating point unit is a FPU implementation different
from the FPU2000 in the following ways:
- it may be configured with only single or with both single and double
precision operations support;
- it may be configured with division and square root opcodes;
- FSR register accumulates inValid, division by Zero, Overflow,
Underflow and Inexact result flags of operations;
- QNaNs and SNaNs are handled properly;
- NaN propagation rules are different.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| -rw-r--r-- | target/xtensa/cpu.h | 2 | ||||
| -rw-r--r-- | target/xtensa/overlay_tool.h | 23 |
2 files changed, 25 insertions, 0 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 960f657344..6fc1565000 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -52,6 +52,8 @@ enum { XTENSA_OPTION_COPROCESSOR, XTENSA_OPTION_BOOLEAN, XTENSA_OPTION_FP_COPROCESSOR, + XTENSA_OPTION_DFP_COPROCESSOR, + XTENSA_OPTION_DFPU_SINGLE_ONLY, XTENSA_OPTION_MP_SYNCHRO, XTENSA_OPTION_CONDITIONAL_STORE, XTENSA_OPTION_ATOMCTL, diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index eb9f08af0b..9f0846c86b 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -39,6 +39,26 @@ #define XCHAL_HAVE_DEPBITS 0 #endif +#ifndef XCHAL_HAVE_DFP +#define XCHAL_HAVE_DFP 0 +#endif + +#ifndef XCHAL_HAVE_DFPU_SINGLE_ONLY +#define XCHAL_HAVE_DFPU_SINGLE_ONLY 0 +#endif + +#ifndef XCHAL_HAVE_DFPU_SINGLE_DOUBLE +#define XCHAL_HAVE_DFPU_SINGLE_DOUBLE XCHAL_HAVE_DFP +#endif + +/* + * We need to know the type of FP unit, not only its precision. + * Unfortunately XCHAL macros don't tell this explicitly. + */ +#define XCHAL_HAVE_DFPU (XCHAL_HAVE_DFP || \ + XCHAL_HAVE_DFPU_SINGLE_ONLY || \ + XCHAL_HAVE_DFPU_SINGLE_DOUBLE) + #ifndef XCHAL_HAVE_DIV32 #define XCHAL_HAVE_DIV32 0 #endif @@ -99,6 +119,9 @@ XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \ XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \ XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \ + XCHAL_OPTION(XCHAL_HAVE_DFPU, XTENSA_OPTION_DFP_COPROCESSOR) | \ + XCHAL_OPTION(XCHAL_HAVE_DFPU_SINGLE_ONLY, \ + XTENSA_OPTION_DFPU_SINGLE_ONLY) | \ XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \ XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \ XCHAL_OPTION(((XCHAL_HAVE_S32C1I && XCHAL_HW_VERSION >= 230000) || \ |