diff options
| author | Dmitry Fleytman <dmitry@daynix.com> | 2016-09-15 09:14:26 +0300 |
|---|---|---|
| committer | Jason Wang <jasowang@redhat.com> | 2016-09-27 17:54:22 +0800 |
| commit | 2d803144a637130b1f167b309bc8ac7142f76b26 (patch) | |
| tree | fe4bc3e6903f0770ec910710ad1e18499ded4b08 | |
| parent | 40364748ddca8a510de5f345b8f7c1c49d24cd26 (diff) | |
e1000e: Fix CTRL_EXT.EIAME behavior
CTRL_EXT.EIAME bit controls clearing of IAM bits,
but current code clears IMS bits instead.
See spec. 10.2.2.5 Extended Device Control Register.
Signed-off-by: Dmitry Fleytman <dmitry@daynix.com>
Signed-off-by: Jason Wang <jasowang@redhat.com>
| -rw-r--r-- | hw/net/e1000e_core.c | 4 | ||||
| -rw-r--r-- | hw/net/trace-events | 2 |
2 files changed, 3 insertions, 3 deletions
diff --git a/hw/net/e1000e_core.c b/hw/net/e1000e_core.c index e8d50f65f0..a198a884ed 100644 --- a/hw/net/e1000e_core.c +++ b/hw/net/e1000e_core.c @@ -2008,8 +2008,8 @@ e1000e_msix_notify_one(E1000ECore *core, uint32_t cause, uint32_t int_cfg) } if (core->mac[CTRL_EXT] & E1000_CTRL_EXT_EIAME) { - trace_e1000e_irq_ims_clear_eiame(core->mac[IAM], cause); - e1000e_clear_ims_bits(core, core->mac[IAM] & cause); + trace_e1000e_irq_iam_clear_eiame(core->mac[IAM], cause); + core->mac[IAM] &= ~cause; } trace_e1000e_irq_icr_clear_eiac(core->mac[ICR], core->mac[EIAC]); diff --git a/hw/net/trace-events b/hw/net/trace-events index 47ab14ac71..1a5c909939 100644 --- a/hw/net/trace-events +++ b/hw/net/trace-events @@ -223,7 +223,7 @@ e1000e_irq_icr_read_entry(uint32_t icr) "Starting ICR read. Current ICR: 0x%x" e1000e_irq_icr_read_exit(uint32_t icr) "Ending ICR read. Current ICR: 0x%x" e1000e_irq_icr_clear_zero_ims(void) "Clearing ICR on read due to zero IMS" e1000e_irq_icr_clear_iame(void) "Clearing ICR on read due to IAME" -e1000e_irq_ims_clear_eiame(uint32_t iam, uint32_t cause) "Clearing IMS due to EIAME, IAM: 0x%X, cause: 0x%X" +e1000e_irq_iam_clear_eiame(uint32_t iam, uint32_t cause) "Clearing IMS due to EIAME, IAM: 0x%X, cause: 0x%X" e1000e_irq_icr_clear_eiac(uint32_t icr, uint32_t eiac) "Clearing ICR bits due to EIAC, ICR: 0x%X, EIAC: 0x%X" e1000e_irq_ims_clear_set_imc(uint32_t val) "Clearing IMS bits due to IMC write 0x%x" e1000e_irq_fire_delayed_interrupts(void) "Firing delayed interrupts" |