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authorRichard Henderson <richard.henderson@linaro.org>2018-05-10 20:31:33 -0700
committerRichard Henderson <richard.henderson@linaro.org>2018-05-18 14:52:38 -0700
commit86ea188012c26a724bfefe0fb9a838ce808993cc (patch)
tree6a3ab2021b8e2a5d5427d317a3aa701a0f75e2b9
parent685f1ce236d93177532f5ec42b130a50809bf171 (diff)
target/riscv: Honor CPU_DUMP_FPU
Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Reviewed-by: Michael Clark <mjc@sifive.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
-rw-r--r--target/riscv/cpu.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 4e5a56d4e3..d630e8fd6c 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -219,11 +219,13 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f,
cpu_fprintf(f, "\n");
}
}
- for (i = 0; i < 32; i++) {
- cpu_fprintf(f, " %s %016" PRIx64,
- riscv_fpr_regnames[i], env->fpr[i]);
- if ((i & 3) == 3) {
- cpu_fprintf(f, "\n");
+ if (flags & CPU_DUMP_FPU) {
+ for (i = 0; i < 32; i++) {
+ cpu_fprintf(f, " %s %016" PRIx64,
+ riscv_fpr_regnames[i], env->fpr[i]);
+ if ((i & 3) == 3) {
+ cpu_fprintf(f, "\n");
+ }
}
}
}