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authorPeter Maydell <peter.maydell@linaro.org>2012-04-13 11:39:07 +0000
committerPeter Maydell <peter.maydell@linaro.org>2012-04-13 11:39:07 +0000
commit496dbcd1a38c2ae4ada848445e4a1aa758af9f43 (patch)
tree8b39a3774273c83b48ee27e5d48fc1c54e998729
parent544d1afa7013fce155f5afbbc24737f2fc0c0f26 (diff)
hw/arm_gic: Make the GIC its own sysbus device
Compile arm_gic.c as a standalone C file to produce a self contained sysbus GIC device. Support the legacy usage by #include of the .c file by making those users #define LEGACY_INCLUDED_GIC, so we can convert them one by one. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Evgeny Voevodin <e.voevodin@samsung.com>
-rw-r--r--Makefile.target1
-rw-r--r--hw/a15mpcore.c1
-rw-r--r--hw/a9mpcore.c1
-rw-r--r--hw/arm11mpcore.c1
-rw-r--r--hw/arm_gic.c52
-rw-r--r--hw/armv7m_nvic.c1
-rw-r--r--hw/exynos4210_gic.c1
-rw-r--r--hw/realview_gic.c1
8 files changed, 58 insertions, 1 deletions
diff --git a/Makefile.target b/Makefile.target
index 1110796e48..0f09180f01 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -365,6 +365,7 @@ obj-arm-y += cadence_uart.o
obj-arm-y += cadence_ttc.o
obj-arm-y += cadence_gem.o
obj-arm-y += xilinx_zynq.o zynq_slcr.o
+obj-arm-y += arm_gic.o
obj-arm-y += realview_gic.o realview.o arm_sysctl.o arm11mpcore.o a9mpcore.o
obj-arm-y += exynos4210_gic.o exynos4210_combiner.o exynos4210.o
obj-arm-y += exynos4_boards.o exynos4210_uart.o exynos4210_pwm.o
diff --git a/hw/a15mpcore.c b/hw/a15mpcore.c
index 2e2ed423da..54c0dbf60e 100644
--- a/hw/a15mpcore.c
+++ b/hw/a15mpcore.c
@@ -20,6 +20,7 @@
#include "sysbus.h"
+#define LEGACY_INCLUDED_GIC
#include "arm_gic.c"
/* A15MP private memory region. */
diff --git a/hw/a9mpcore.c b/hw/a9mpcore.c
index 1d83c37ad5..164a0d359c 100644
--- a/hw/a9mpcore.c
+++ b/hw/a9mpcore.c
@@ -10,6 +10,7 @@
#include "sysbus.h"
+#define LEGACY_INCLUDED_GIC
#include "arm_gic.c"
/* A9MP private memory region. */
diff --git a/hw/arm11mpcore.c b/hw/arm11mpcore.c
index c4829d8845..e876a0edc8 100644
--- a/hw/arm11mpcore.c
+++ b/hw/arm11mpcore.c
@@ -10,6 +10,7 @@
#include "sysbus.h"
#include "qemu-timer.h"
+#define LEGACY_INCLUDED_GIC
#include "arm_gic.c"
/* MPCore private memory region. */
diff --git a/hw/arm_gic.c b/hw/arm_gic.c
index fabbcc5d63..b54357033b 100644
--- a/hw/arm_gic.c
+++ b/hw/arm_gic.c
@@ -11,6 +11,8 @@
controller, MPCore distributed interrupt controller and ARMv7-M
Nested Vectored Interrupt Controller. */
+#include "sysbus.h"
+
/* Maximum number of possible interrupts, determined by the GIC architecture */
#define GIC_MAXIRQ 1020
/* First 32 are private to each CPU (SGIs and PPIs). */
@@ -112,7 +114,7 @@ typedef struct gic_state
int current_pending[NCPU];
#if NCPU > 1
- int num_cpu;
+ uint32_t num_cpu;
#endif
MemoryRegion iomem; /* Distributor */
@@ -906,3 +908,51 @@ static void gic_init(gic_state *s, int num_irq)
gic_reset(s);
register_savevm(NULL, "arm_gic", -1, 2, gic_save, gic_load, s);
}
+
+#ifndef LEGACY_INCLUDED_GIC
+
+static int arm_gic_init(SysBusDevice *dev)
+{
+ /* Device instance init function for the GIC sysbus device */
+ int i;
+ gic_state *s = FROM_SYSBUS(gic_state, dev);
+ gic_init(s, s->num_cpu, s->num_irq);
+ /* Distributor */
+ sysbus_init_mmio(dev, &s->iomem);
+ /* cpu interfaces (one for "current cpu" plus one per cpu) */
+ for (i = 0; i <= NUM_CPU(s); i++) {
+ sysbus_init_mmio(dev, &s->cpuiomem[i]);
+ }
+ return 0;
+}
+
+static Property arm_gic_properties[] = {
+ DEFINE_PROP_UINT32("num-cpu", gic_state, num_cpu, 1),
+ DEFINE_PROP_UINT32("num-irq", gic_state, num_irq, 32),
+ DEFINE_PROP_END_OF_LIST(),
+};
+
+static void arm_gic_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
+ sbc->init = arm_gic_init;
+ dc->props = arm_gic_properties;
+ dc->no_user = 1;
+}
+
+static TypeInfo arm_gic_info = {
+ .name = "arm_gic",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(gic_state),
+ .class_init = arm_gic_class_init,
+};
+
+static void arm_gic_register_types(void)
+{
+ type_register_static(&arm_gic_info);
+}
+
+type_init(arm_gic_register_types)
+
+#endif
diff --git a/hw/armv7m_nvic.c b/hw/armv7m_nvic.c
index 99ed85b163..79cf448678 100644
--- a/hw/armv7m_nvic.c
+++ b/hw/armv7m_nvic.c
@@ -16,6 +16,7 @@
#include "exec-memory.h"
#define NVIC 1
+#define LEGACY_INCLUDED_GIC
static uint32_t nvic_readl(void *opaque, uint32_t offset);
static void nvic_writel(void *opaque, uint32_t offset, uint32_t value);
diff --git a/hw/exynos4210_gic.c b/hw/exynos4210_gic.c
index ff7ab848e5..a05dab2d2e 100644
--- a/hw/exynos4210_gic.c
+++ b/hw/exynos4210_gic.c
@@ -262,6 +262,7 @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit)
/********* GIC part *********/
+#define LEGACY_INCLUDED_GIC
#include "arm_gic.c"
typedef struct {
diff --git a/hw/realview_gic.c b/hw/realview_gic.c
index aa780fe47f..a3b5a0472b 100644
--- a/hw/realview_gic.c
+++ b/hw/realview_gic.c
@@ -9,6 +9,7 @@
#include "sysbus.h"
+#define LEGACY_INCLUDED_GIC
#include "arm_gic.c"
typedef struct {