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authorEdgar E. Iglesias <edgar.iglesias@petalogix.com>2011-08-25 16:41:18 +1000
committerEdgar E. Iglesias <edgar.iglesias@gmail.com>2011-08-25 22:44:25 +0200
commit97b833c5df820acc5c7b3e63c84059857c115c45 (patch)
tree7d0faccb05b11273d2c3c93cead9f3f5f7d70771
parent01e0451a08e0afb9af04783c320d70084cf4e574 (diff)
microblaze: Make the MSR PVR bit non writable
Instead of hardcoding it to 1. Signed-off-by: Edgar E. Iglesias <edgar.iglesias@petalogix.com>
-rw-r--r--target-microblaze/translate.c11
1 files changed, 8 insertions, 3 deletions
diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
index 1a862d31e3..15f1fe5cf0 100644
--- a/target-microblaze/translate.c
+++ b/target-microblaze/translate.c
@@ -424,10 +424,15 @@ static inline void msr_read(DisasContext *dc, TCGv d)
static inline void msr_write(DisasContext *dc, TCGv v)
{
+ TCGv t;
+
+ t = tcg_temp_new();
dc->cpustate_changed = 1;
- tcg_gen_mov_tl(cpu_SR[SR_MSR], v);
- /* PVR, we have a processor version register. */
- tcg_gen_ori_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10));
+ /* PVR bit is not writable. */
+ tcg_gen_andi_tl(t, v, ~(1 << 10));
+ tcg_gen_andi_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], (1 << 10));
+ tcg_gen_or_tl(cpu_SR[SR_MSR], cpu_SR[SR_MSR], v);
+ tcg_temp_free(t);
}
static void dec_msr(DisasContext *dc)