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authorRichard Henderson <richard.henderson@linaro.org>2019-11-19 13:20:28 +0000
committerPeter Maydell <peter.maydell@linaro.org>2019-11-19 13:20:28 +0000
commit655b02646dc175dc10666459b0a1e4346fc8d46a (patch)
treeeacbc2b33d8153c461bddf9463eec1f0c2c3cec7
parent6623d214451ec4f784d1c82c51c655a01fed1b06 (diff)
target/arm: Do not reject rt == rt2 for strexd
There was too much cut and paste between ldrexd and strexd, as ldrexd does prohibit two output registers the same. Fixes: af288228995 Reported-by: Michael Goffioul <michael.goffioul@gmail.com> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20191117090621.32425-2-richard.henderson@linaro.org Reviewed-by: Robert Foley <robert.foley@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r--target/arm/translate.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 2ea9da7637..b285b23858 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -8934,7 +8934,7 @@ static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel)
|| (s->thumb && (a->rd == 13 || a->rt == 13))
|| (mop == MO_64
&& (a->rt2 == 15
- || a->rd == a->rt2 || a->rt == a->rt2
+ || a->rd == a->rt2
|| (s->thumb && a->rt2 == 13)))) {
unallocated_encoding(s);
return true;