diff options
| author | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-10-13 23:42:37 +0200 |
|---|---|---|
| committer | Philippe Mathieu-Daudé <f4bug@amsat.org> | 2021-10-18 00:41:36 +0200 |
| commit | 0e235827de65b8a0a5fa403ad9ed15d04f8b1a4f (patch) | |
| tree | c318321d22783dd0c059ee18d413deedc13fb90f | |
| parent | d2db0f729da6946873b1352bfb7c12c2c9f91fb0 (diff) | |
target/mips: Fix DEXTRV_S.H DSP opcode
While for the DEXTR_S.H opcode:
"The shift argument is provided in the instruction."
For the DEXTRV_S.H opcode we have:
"The five least-significant bits of register rs provide the
shift argument, interpreted as a five-bit unsigned integer;
the remaining bits in rs are ignored."
While 't1' contains the 'rs' register content (the shift value
for DEXTR_S.H), we need to load the value of 'rs' for DEXTRV_S.H.
We can directly use the v1_t TCG register which already contains
this shift value.
Fixes: b53371ed5d4 ("target-mips: Add ASE DSP accumulator instructions")
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20211013215652.1764551-1-f4bug@amsat.org>
| -rw-r--r-- | target/mips/tcg/translate.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/target/mips/tcg/translate.c b/target/mips/tcg/translate.c index 5fdeb67e82..519b00121f 100644 --- a/target/mips/tcg/translate.c +++ b/target/mips/tcg/translate.c @@ -13796,8 +13796,7 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, break; case OPC_DEXTRV_S_H: tcg_gen_movi_tl(t0, v2); - tcg_gen_movi_tl(t1, v1); - gen_helper_dextr_s_h(cpu_gpr[ret], t0, t1, cpu_env); + gen_helper_dextr_s_h(cpu_gpr[ret], t0, v1_t, cpu_env); break; case OPC_DEXTRV_L: tcg_gen_movi_tl(t0, v2); |