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authorAlexander Graf <agraf@suse.de>2011-07-21 01:39:46 +0200
committerAlexander Graf <agraf@suse.de>2011-10-06 09:43:33 +0200
commitbbc5842211cdd90103cfe52f2ca24afac880694f (patch)
treec06a416d4efccc8856edc088c5b34661ee388e7b
parent0d33defbe3e75db75599c52607da6fc3b4ce0f25 (diff)
PPC: Bump MPIC up to 32 supported CPUs
The MPIC emulation is now capable of handling up to 32 CPUs. Reflect that in the code exporting the numbers out and fix an integer overflow while at it. Signed-off-by: Alexander Graf <agraf@suse.de> --- v1 -> v2: - Max cpus is 15 due to cINT routing - Report nb_cpus not MAX_CPUS in MPIC capabilities
-rw-r--r--hw/openpic.c10
1 files changed, 3 insertions, 7 deletions
diff --git a/hw/openpic.c b/hw/openpic.c
index 109c1bc6f4..03e442b1f5 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -63,7 +63,7 @@
#elif defined(USE_MPCxxx)
-#define MAX_CPU 2
+#define MAX_CPU 15
#define MAX_IRQ 128
#define MAX_DBL 0
#define MAX_MBX 0
@@ -507,7 +507,7 @@ static inline void write_IRQreg (openpic_t *opp, int n_IRQ,
break;
case IRQ_IDE:
tmp = val & 0xC0000000;
- tmp |= val & ((1 << MAX_CPU) - 1);
+ tmp |= val & ((1ULL << MAX_CPU) - 1);
opp->src[n_IRQ].ide = tmp;
DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
break;
@@ -1283,7 +1283,7 @@ static void mpic_reset (void *opaque)
mpp->glbc = 0x80000000;
/* Initialise controller registers */
- mpp->frep = 0x004f0002;
+ mpp->frep = 0x004f0002 | ((mpp->nb_cpus - 1) << 8);
mpp->veni = VENI;
mpp->pint = 0x00000000;
mpp->spve = 0x0000FFFF;
@@ -1684,10 +1684,6 @@ qemu_irq *mpic_init (target_phys_addr_t base, int nb_cpus,
{mpic_cpu_read, mpic_cpu_write, MPIC_CPU_REG_START, MPIC_CPU_REG_SIZE},
};
- /* XXX: for now, only one CPU is supported */
- if (nb_cpus != 1)
- return NULL;
-
mpp = g_malloc0(sizeof(openpic_t));
for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {