diff options
| author | Paul Brook <paul@codesourcery.com> | 2010-03-12 16:54:58 +0000 |
|---|---|---|
| committer | Paul Brook <paul@codesourcery.com> | 2010-03-12 18:34:21 +0000 |
| commit | 20cb400d41b07f33ed34d5ed917e534c7f12738b (patch) | |
| tree | 48cd594d36f4d3a91f8aaced83a4ed99ca1c67df | |
| parent | 41c1b1c9ebb45b97795fa9e58eaa6fedc4eafe0e (diff) | |
Remove TLB from userspace
Remove TLB from userspace CPU structure.
Signed-off-by: Paul Brook <paul@codesourcery.com>
| -rw-r--r-- | cpu-defs.h | 17 | ||||
| -rw-r--r-- | tcg/arm/tcg-target.c | 2 | ||||
| -rw-r--r-- | tcg/i386/tcg-target.c | 2 | ||||
| -rw-r--r-- | tcg/x86_64/tcg-target.c | 2 |
4 files changed, 20 insertions, 3 deletions
diff --git a/cpu-defs.h b/cpu-defs.h index 7fdbe97787..47c1d85968 100644 --- a/cpu-defs.h +++ b/cpu-defs.h @@ -72,6 +72,7 @@ typedef uint64_t target_ulong; #define TB_JMP_ADDR_MASK (TB_JMP_PAGE_SIZE - 1) #define TB_JMP_PAGE_MASK (TB_JMP_CACHE_SIZE - TB_JMP_PAGE_SIZE) +#if !defined(CONFIG_USER_ONLY) #define CPU_TLB_BITS 8 #define CPU_TLB_SIZE (1 << CPU_TLB_BITS) @@ -106,6 +107,18 @@ typedef struct CPUTLBEntry { sizeof(target_phys_addr_t))]; } CPUTLBEntry; +#define CPU_COMMON_TLB \ + /* The meaning of the MMU modes is defined in the target code. */ \ + CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ + target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ + +#else + +#define CPU_COMMON_TLB + +#endif + + #ifdef HOST_WORDS_BIGENDIAN typedef struct icount_decr_u16 { uint16_t high; @@ -150,9 +163,7 @@ typedef struct CPUWatchpoint { uint32_t stopped; /* Artificially stopped */ \ uint32_t interrupt_request; \ volatile sig_atomic_t exit_request; \ - /* The meaning of the MMU modes is defined in the target code. */ \ - CPUTLBEntry tlb_table[NB_MMU_MODES][CPU_TLB_SIZE]; \ - target_phys_addr_t iotlb[NB_MMU_MODES][CPU_TLB_SIZE]; \ + CPU_COMMON_TLB \ struct TranslationBlock *tb_jmp_cache[TB_JMP_CACHE_SIZE]; \ /* buffer for temporaries in the code generator */ \ long temp_buf[CPU_TEMP_BUF_NLONGS]; \ diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index dabc0f5bca..6d1ea14def 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -1690,9 +1690,11 @@ static const TCGTargetOpDef arm_op_defs[] = { void tcg_target_init(TCGContext *s) { +#if !defined(CONFIG_USER_ONLY) /* fail safe */ if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry)) tcg_abort(); +#endif tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, ((2 << TCG_REG_R14) - 1) & ~(1 << TCG_REG_R8)); diff --git a/tcg/i386/tcg-target.c b/tcg/i386/tcg-target.c index b69b5b0c8c..09c73b4396 100644 --- a/tcg/i386/tcg-target.c +++ b/tcg/i386/tcg-target.c @@ -1353,9 +1353,11 @@ void tcg_target_qemu_prologue(TCGContext *s) void tcg_target_init(TCGContext *s) { +#if !defined(CONFIG_USER_ONLY) /* fail safe */ if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry)) tcg_abort(); +#endif tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xff); tcg_regset_set32(tcg_target_call_clobber_regs, 0, diff --git a/tcg/x86_64/tcg-target.c b/tcg/x86_64/tcg-target.c index 6e7a6a42f9..ea313fa87a 100644 --- a/tcg/x86_64/tcg-target.c +++ b/tcg/x86_64/tcg-target.c @@ -1426,9 +1426,11 @@ static const TCGTargetOpDef x86_64_op_defs[] = { void tcg_target_init(TCGContext *s) { +#if !defined(CONFIG_USER_ONLY) /* fail safe */ if ((1 << CPU_TLB_ENTRY_BITS) != sizeof(CPUTLBEntry)) tcg_abort(); +#endif tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0, 0xffff); |