diff options
| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-01-25 19:52:54 +0000 |
|---|---|---|
| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-01-25 19:52:54 +0000 |
| commit | e5e38121576e57ea4f1f4acae01f58f0386ff0ba (patch) | |
| tree | 34ff954d1d508a787b862f89cf4ae0e061bedc19 | |
| parent | e1cb9502426a605e30aa4a43875161ee44a66bc2 (diff) | |
Add TurboSPARC mask ID register (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3932 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | hw/iommu.c | 12 |
1 files changed, 11 insertions, 1 deletions
diff --git a/hw/iommu.c b/hw/iommu.c index f83a9e3efc..440847f2b2 100644 --- a/hw/iommu.c +++ b/hw/iommu.c @@ -34,7 +34,7 @@ do { printf("IOMMU: " fmt , ##args); } while (0) #define DPRINTF(fmt, args...) #endif -#define IOMMU_NREGS (3*4096/4) +#define IOMMU_NREGS (4*4096/4) #define IOMMU_CTRL (0x0000 >> 2) #define IOMMU_CTRL_IMPL 0xf0000000 /* Implementation */ #define IOMMU_CTRL_VERS 0x0f000000 /* Version */ @@ -95,6 +95,12 @@ do { printf("IOMMU: " fmt , ##args); } while (0) #define IOMMU_ARBEN_MASK 0x001f0000 #define IOMMU_MID 0x00000008 +#define IOMMU_MASK_ID (0x3018 >> 2) /* Mask ID */ +#define IOMMU_MASK_ID_MASK 0x00ffffff + +#define IOMMU_MSII_MASK 0x26000000 /* microSPARC II mask number */ +#define IOMMU_TS_MASK 0x23000000 /* turboSPARC mask number */ + /* The format of an iopte in the page tables */ #define IOPTE_PAGE 0xffffff00 /* Physical page number (PA[35:12]) */ #define IOPTE_CACHE 0x00000080 /* Cached (in vme IOCACHE or @@ -206,6 +212,9 @@ static void iommu_mem_writel(void *opaque, target_phys_addr_t addr, // addresses, fault cause and address stored to MMU/IOMMU s->regs[saddr] = (val & IOMMU_ARBEN_MASK) | IOMMU_MID; break; + case IOMMU_MASK_ID: + s->regs[saddr] |= val & IOMMU_MASK_ID_MASK; + break; default: s->regs[saddr] = val; break; @@ -337,6 +346,7 @@ static void iommu_reset(void *opaque) s->regs[IOMMU_CTRL] = s->version; s->regs[IOMMU_ARBEN] = IOMMU_MID; s->regs[IOMMU_AFSR] = IOMMU_AFSR_RESV; + s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK; qemu_irq_lower(s->irq); } |