diff options
| author | Richard Henderson <rth@twiddle.net> | 2016-11-16 17:36:51 +0100 |
|---|---|---|
| committer | Richard Henderson <rth@twiddle.net> | 2017-01-10 08:47:48 -0800 |
| commit | 16256947eb30b3433839b536bd689be1d2bea5d8 (patch) | |
| tree | 1870d6fdc369f72e19582981a20506fe8a367972 | |
| parent | bc21dbcc1203ae6bb536f832c46a3b5e22a73451 (diff) | |
target-tricore: Use clrsb helper
Tested-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Reviewed-by: Bastian Koppelmann <kbastian@mail.uni-paderborn.de>
Signed-off-by: Richard Henderson <rth@twiddle.net>
| -rw-r--r-- | target/tricore/helper.h | 1 | ||||
| -rw-r--r-- | target/tricore/op_helper.c | 5 | ||||
| -rw-r--r-- | target/tricore/translate.c | 2 |
3 files changed, 1 insertions, 7 deletions
diff --git a/target/tricore/helper.h b/target/tricore/helper.h index 2cf04e1b11..d215349bb8 100644 --- a/target/tricore/helper.h +++ b/target/tricore/helper.h @@ -89,7 +89,6 @@ DEF_HELPER_FLAGS_2(ixmin_u, TCG_CALL_NO_RWG_SE, i64, i64, i32) /* count leading ... */ DEF_HELPER_FLAGS_1(clo_h, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_1(clz_h, TCG_CALL_NO_RWG_SE, i32, i32) -DEF_HELPER_FLAGS_1(cls, TCG_CALL_NO_RWG_SE, i32, i32) DEF_HELPER_FLAGS_1(cls_h, TCG_CALL_NO_RWG_SE, i32, i32) /* sh */ DEF_HELPER_FLAGS_2(sh, TCG_CALL_NO_RWG_SE, i32, i32, i32) diff --git a/target/tricore/op_helper.c b/target/tricore/op_helper.c index 3731d5e6f1..7af202c8c0 100644 --- a/target/tricore/op_helper.c +++ b/target/tricore/op_helper.c @@ -1769,11 +1769,6 @@ uint32_t helper_clz_h(target_ulong r1) return ret_hw0 | (ret_hw1 << 16); } -uint32_t helper_cls(target_ulong r1) -{ - return clrsb32(r1); -} - uint32_t helper_cls_h(target_ulong r1) { uint32_t ret_hw0 = extract32(r1, 0, 16); diff --git a/target/tricore/translate.c b/target/tricore/translate.c index 69cdfb9177..41b1d27352 100644 --- a/target/tricore/translate.c +++ b/target/tricore/translate.c @@ -6374,7 +6374,7 @@ static void decode_rr_logical_shift(CPUTriCoreState *env, DisasContext *ctx) gen_helper_clo_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); break; case OPC2_32_RR_CLS: - gen_helper_cls(cpu_gpr_d[r3], cpu_gpr_d[r1]); + tcg_gen_clrsb_tl(cpu_gpr_d[r3], cpu_gpr_d[r1]); break; case OPC2_32_RR_CLS_H: gen_helper_cls_h(cpu_gpr_d[r3], cpu_gpr_d[r1]); |