diff options
| author | Peter Maydell <peter.maydell@linaro.org> | 2016-02-11 11:17:31 +0000 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2016-02-11 11:17:31 +0000 |
| commit | 4df322593037d2700f72dfdfb967300b7ad2e696 (patch) | |
| tree | 105f55d22619a99fbe62b89ba824a73dfec4b04b | |
| parent | fc05f4a62c568b607ec3fe428a419bb38205b570 (diff) | |
target-arm: Fix IL bit reported for Thumb coprocessor traps
All Thumb coprocessor instructions are 32 bits, so the IL
bit in the syndrome register should be set. Pass false to the
syn_* function's is_16bit argument rather than s->thumb
so we report the correct IL bit.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Sergey Fedorov <serge.fdrv@gmail.com>
Message-id: 1454683067-16001-3-git-send-email-peter.maydell@linaro.org
| -rw-r--r-- | target-arm/translate.c | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/target-arm/translate.c b/target-arm/translate.c index 2c8213b07a..8e8ffee9c6 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -7184,19 +7184,19 @@ static int disas_coproc_insn(DisasContext *s, uint32_t insn) case 14: if (is64) { syndrome = syn_cp14_rrt_trap(1, 0xe, opc1, crm, rt, rt2, - isread, s->thumb); + isread, false); } else { syndrome = syn_cp14_rt_trap(1, 0xe, opc1, opc2, crn, crm, - rt, isread, s->thumb); + rt, isread, false); } break; case 15: if (is64) { syndrome = syn_cp15_rrt_trap(1, 0xe, opc1, crm, rt, rt2, - isread, s->thumb); + isread, false); } else { syndrome = syn_cp15_rt_trap(1, 0xe, opc1, opc2, crn, crm, - rt, isread, s->thumb); + rt, isread, false); } break; default: |