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authorPeter Maydell <peter.maydell@linaro.org>2014-06-19 18:06:24 +0100
committerPeter Maydell <peter.maydell@linaro.org>2014-06-19 18:06:24 +0100
commit5661ae6be23d8831a19c82f8eafb2aaecdf2da6a (patch)
tree77fb3fd29588ffcfde49ef24492d5108ecb8ecb2
parent0062609f70b465a56cf80bc573d0971ef2a0affb (diff)
target-arm: Add ULL suffix to calculation of page size
The maximum block size for AArch64 address translation is 2GB. This means that we need a ULL suffix on our shift to avoid shifting into the sign bit of a signed 32 bit integer. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Message-id: 1402171881-14343-2-git-send-email-peter.maydell@linaro.org
-rw-r--r--target-arm/helper.c2
1 files changed, 1 insertions, 1 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c
index 12285cdb6c..ed4d2bb419 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -3952,7 +3952,7 @@ static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
* These are basically the same thing, although the number
* of bits we pull in from the vaddr varies.
*/
- page_size = (1 << ((granule_sz * (4 - level)) + 3));
+ page_size = (1ULL << ((granule_sz * (4 - level)) + 3));
descaddr |= (address & (page_size - 1));
/* Extract attributes from the descriptor and merge with table attrs */
attrs = extract64(descriptor, 2, 10)