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authorblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2008-07-16 16:55:52 +0000
committerblueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162>2008-07-16 16:55:52 +0000
commite19e4efeaa250e269b491f3a04e04a35831d313a (patch)
treecc9a72bcd4e2c23e5364d089e7ff0b38f85d4d3a
parent477b24ef911753e1debbacf798242a06de0af96c (diff)
Fix MMU miss traps
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4880 c046a42c-6fe2-441c-8c8c-71466251a162
-rw-r--r--target-sparc/cpu.h4
-rw-r--r--target-sparc/helper.c4
2 files changed, 4 insertions, 4 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h
index 937ce6f96f..9121682e74 100644
--- a/target-sparc/cpu.h
+++ b/target-sparc/cpu.h
@@ -50,7 +50,6 @@
#define TT_TRAP 0x80
#else
#define TT_TFAULT 0x08
-#define TT_TMISS 0x09
#define TT_CODE_ACCESS 0x0a
#define TT_ILL_INSN 0x10
#define TT_UNIMP_FLUSH TT_ILL_INSN
@@ -61,12 +60,13 @@
#define TT_CLRWIN 0x24
#define TT_DIV_ZERO 0x28
#define TT_DFAULT 0x30
-#define TT_DMISS 0x31
#define TT_DATA_ACCESS 0x32
#define TT_DPROT 0x33
#define TT_UNALIGNED 0x34
#define TT_PRIV_ACT 0x37
#define TT_EXTINT 0x40
+#define TT_TMISS 0x64
+#define TT_DMISS 0x68
#define TT_SPILL 0x80
#define TT_FILL 0xc0
#define TT_WOTHER 0x10
diff --git a/target-sparc/helper.c b/target-sparc/helper.c
index 1cfe170de4..14364fb91f 100644
--- a/target-sparc/helper.c
+++ b/target-sparc/helper.c
@@ -655,7 +655,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
#ifdef TARGET_SPARC64
#ifdef DEBUG_PCALL
-static const char * const excp_names[0x50] = {
+static const char * const excp_names[0x80] = {
[TT_TFAULT] = "Instruction Access Fault",
[TT_TMISS] = "Instruction Access MMU Miss",
[TT_CODE_ACCESS] = "Instruction Access Error",
@@ -699,7 +699,7 @@ void do_interrupt(CPUState *env)
static int count;
const char *name;
- if (intno < 0 || intno >= 0x180 || (intno > 0x4f && intno < 0x80))
+ if (intno < 0 || intno >= 0x180)
name = "Unknown";
else if (intno >= 0x100)
name = "Trap Instruction";