diff options
author | Bin Meng <bin.meng@windriver.com> | 2020-07-09 03:05:43 -0700 |
---|---|---|
committer | Alistair Francis <alistair.francis@wdc.com> | 2020-07-13 17:25:37 -0700 |
commit | 9eb8b14a70e57bc1449afc08aa4bf3131ee680d8 (patch) | |
tree | 90c929a77f1d618413f830bc4b8f9fb8005b8249 | |
parent | 8590f53661ec678fd3aa97b4da212b0c00056c2e (diff) |
hw/riscv: Modify MROM size to end at 0x10000
At present the size of Mask ROM for sifive_u / spike / virt machines
is set to 0x11000, which ends at an unusual address. This changes the
size to 0xf000 so that it ends at 0x10000.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <1594289144-24723-1-git-send-email-bmeng.cn@gmail.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
-rw-r--r-- | hw/riscv/sifive_u.c | 2 | ||||
-rw-r--r-- | hw/riscv/spike.c | 2 | ||||
-rw-r--r-- | hw/riscv/virt.c | 2 |
3 files changed, 3 insertions, 3 deletions
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6595ab3f87..19a976c9a6 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -70,7 +70,7 @@ static const struct MemmapEntry { hwaddr size; } sifive_u_memmap[] = { [SIFIVE_U_DEBUG] = { 0x0, 0x100 }, - [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, + [SIFIVE_U_MROM] = { 0x1000, 0xf000 }, [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, [SIFIVE_U_L2LIM] = { 0x8000000, 0x2000000 }, [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index b17d96aec7..7b23a297fc 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -52,7 +52,7 @@ static const struct MemmapEntry { hwaddr base; hwaddr size; } spike_memmap[] = { - [SPIKE_MROM] = { 0x1000, 0x11000 }, + [SPIKE_MROM] = { 0x1000, 0xf000 }, [SPIKE_CLINT] = { 0x2000000, 0x10000 }, [SPIKE_DRAM] = { 0x80000000, 0x0 }, }; diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index bc25ec69f7..55a907bb35 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -53,7 +53,7 @@ static const struct MemmapEntry { hwaddr size; } virt_memmap[] = { [VIRT_DEBUG] = { 0x0, 0x100 }, - [VIRT_MROM] = { 0x1000, 0x11000 }, + [VIRT_MROM] = { 0x1000, 0xf000 }, [VIRT_TEST] = { 0x100000, 0x1000 }, [VIRT_RTC] = { 0x101000, 0x1000 }, [VIRT_CLINT] = { 0x2000000, 0x10000 }, |