diff options
| author | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-23 15:30:50 +0000 |
|---|---|---|
| committer | blueswir1 <blueswir1@c046a42c-6fe2-441c-8c8c-71466251a162> | 2008-12-23 15:30:50 +0000 |
| commit | 4017190e2d75882a0e9dbc40f403e584e0ab46c4 (patch) | |
| tree | 8fa9cec975d8f2afd8449ca08947177326afc442 | |
| parent | 0bb3602c44b73c647b8a478d7077192a576b5781 (diff) | |
Add SuperSPARC MMU breakpoint registers (Robert Reif)
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6125 c046a42c-6fe2-441c-8c8c-71466251a162
| -rw-r--r-- | target-sparc/cpu.h | 1 | ||||
| -rw-r--r-- | target-sparc/op_helper.c | 45 |
2 files changed, 45 insertions, 1 deletions
diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 136319c5c4..1fb249b65a 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -301,6 +301,7 @@ typedef struct CPUSPARCState { uint32_t mmuregs[32]; uint64_t mxccdata[4]; uint64_t mxccregs[8]; + uint64_t mmubpregs[4]; uint64_t prom_addr; #endif /* temporary float registers */ diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index 15f259da24..0cde695869 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -953,6 +953,28 @@ uint64_t helper_ld_asi(target_ulong addr, int asi, int size, int sign) case 0x39: /* data cache diagnostic register */ ret = 0; break; + case 0x38: /* SuperSPARC MMU Breakpoint Control Registers */ + { + int reg = (addr >> 8) & 3; + + switch(reg) { + case 0: /* Breakpoint Value (Addr) */ + ret = env->mmubpregs[reg]; + break; + case 1: /* Breakpoint Mask */ + ret = env->mmubpregs[reg]; + break; + case 2: /* Breakpoint Control */ + ret = env->mmubpregs[reg]; + break; + case 3: /* Breakpoint Status */ + ret = env->mmubpregs[reg]; + env->mmubpregs[reg] = 0ULL; + break; + } + DPRINTF_MMU("read breakpoint reg[%d] 0x%016llx\n", reg, ret); + } + break; case 8: /* User code access, XXX */ default: do_unassigned_access(addr, 0, 0, asi, size); @@ -1283,9 +1305,30 @@ void helper_st_asi(target_ulong addr, uint64_t val, int asi, int size) // descriptor diagnostic case 0x36: /* I-cache flash clear */ case 0x37: /* D-cache flash clear */ - case 0x38: /* breakpoint diagnostics */ case 0x4c: /* breakpoint action */ break; + case 0x38: /* SuperSPARC MMU Breakpoint Control Registers*/ + { + int reg = (addr >> 8) & 3; + + switch(reg) { + case 0: /* Breakpoint Value (Addr) */ + env->mmubpregs[reg] = (val & 0xfffffffffULL); + break; + case 1: /* Breakpoint Mask */ + env->mmubpregs[reg] = (val & 0xfffffffffULL); + break; + case 2: /* Breakpoint Control */ + env->mmubpregs[reg] = (val & 0x7fULL); + break; + case 3: /* Breakpoint Status */ + env->mmubpregs[reg] = (val & 0xfULL); + break; + } + DPRINTF_MMU("write breakpoint reg[%d] 0x%016llx\n", reg, + env->mmuregs[reg]); + } + break; case 8: /* User code access, XXX */ case 9: /* Supervisor code access, XXX */ default: |