diff options
| author | Yongbok Kim <yongbok.kim@imgtec.com> | 2014-11-07 10:43:21 +0000 |
|---|---|---|
| committer | Leon Alrae <leon.alrae@imgtec.com> | 2014-11-07 14:15:28 +0000 |
| commit | cb269f273fdbdb26ddb1cba4a0fe2249418a8e77 (patch) | |
| tree | f2709af757f8049c2562fe69b5e2e00ad82599d6 | |
| parent | 342368aff7d61a32b5853068b92039a2b15507c5 (diff) | |
target-mips: fix multiple TCG registers covering same data
Avoid to allocate different TCG registers for the FPU registers
that are mapped on the MSA vectore registers.
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
| -rw-r--r-- | target-mips/translate.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/target-mips/translate.c b/target-mips/translate.c index 0bea3c44cb..f0b8e6ffe4 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -19285,14 +19285,12 @@ void mips_tcg_init(void) regnames[i]); for (i = 0; i < 32; i++) { - int off = offsetof(CPUMIPSState, active_fpu.fpr[i]); - fpu_f64[i] = tcg_global_mem_new_i64(TCG_AREG0, off, fregnames[i]); - } - - for (i = 0; i < 32; i++) { int off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[0]); msa_wr_d[i * 2] = tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2]); + /* The scalar floating-point unit (FPU) registers are mapped on + * the MSA vector registers. */ + fpu_f64[i] = msa_wr_d[i * 2]; off = offsetof(CPUMIPSState, active_fpu.fpr[i].wr.d[1]); msa_wr_d[i * 2 + 1] = tcg_global_mem_new_i64(TCG_AREG0, off, msaregnames[i * 2 + 1]); |