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| author | Max Filippov <jcmvbkbc@gmail.com> | 2019-02-18 07:12:37 -0800 |
|---|---|---|
| committer | Max Filippov <jcmvbkbc@gmail.com> | 2019-02-28 04:43:23 -0800 |
| commit | 9b2d08a066b85315fa41a3bbe8cc2186278c0f79 (patch) | |
| tree | 490683d39247cb2146894a4e3d9abf773cc95bc7 | |
| parent | 50d3a0feaec5a88d5b3c1235fd058ff19f489885 (diff) | |
tests/tcg/xtensa: fix SR tests for big endian configs
SR tests generate instructions that the assembler does not recognize and
thus must take care about configuration endianness.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
| -rw-r--r-- | tests/tcg/xtensa/test_sr.S | 20 |
1 files changed, 16 insertions, 4 deletions
diff --git a/tests/tcg/xtensa/test_sr.S b/tests/tcg/xtensa/test_sr.S index e64653b877..b1a91a0637 100644 --- a/tests/tcg/xtensa/test_sr.S +++ b/tests/tcg/xtensa/test_sr.S @@ -2,11 +2,23 @@ test_suite sr +#if XCHAL_HAVE_BE +#define LOW__SR 0x04 +#define HI_RSR 0x30 +#define HI_WSR 0x31 +#define HI_XSR 0x16 +#else +#define LOW__SR 0x40 +#define HI_RSR 0x03 +#define HI_WSR 0x13 +#define HI_XSR 0x61 +#endif + .macro sr_op sym, op_sym, op_byte, sr .if \sym \op_sym a4, \sr .else - .byte 0x40, \sr, \op_byte + .byte LOW__SR, \sr, \op_byte .endif .endm @@ -32,9 +44,9 @@ test_suite sr .macro test_sr_mask sr, sym, mask test \sr - test_sr_op \sym, \mask & 1, rsr, 0x03, \sr - test_sr_op \sym, \mask & 2, wsr, 0x13, \sr - test_sr_op \sym, \mask & 4, xsr, 0x61, \sr + test_sr_op \sym, \mask & 1, rsr, HI_RSR, \sr + test_sr_op \sym, \mask & 2, wsr, HI_WSR, \sr + test_sr_op \sym, \mask & 4, xsr, HI_XSR, \sr test_end .endm |