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authorScott Wood <scottwood@freescale.com>2012-12-13 16:12:02 +0000
committerAlexander Graf <agraf@suse.de>2013-01-07 17:37:09 +0100
commitc3203fa5b2c17a1c446e44c87788fef21b4af5f4 (patch)
tree59917bb41d525abe83acc3e41e60a93840645fa7
parenta26a7b38331dc14893a66fbe78f34afab153d6b2 (diff)
openpic: don't crash on a register access without a CPU context
If we access a register via the QEMU memory inspection commands (e.g. "xp") rather than from guest code, we won't have a CPU context. Gracefully fail to access the register in that case, rather than crashing. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Alexander Graf <agraf@suse.de>
-rw-r--r--hw/openpic.c16
1 files changed, 15 insertions, 1 deletions
diff --git a/hw/openpic.c b/hw/openpic.c
index 10dbdf7863..93e8208075 100644
--- a/hw/openpic.c
+++ b/hw/openpic.c
@@ -161,7 +161,11 @@ static inline int test_bit(uint32_t *field, int bit)
static int get_current_cpu(void)
{
- return cpu_single_env->cpu_index;
+ if (!cpu_single_env) {
+ return -1;
+ }
+
+ return cpu_single_env->cpu_index;
}
static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
@@ -810,6 +814,11 @@ static void openpic_cpu_write_internal(void *opaque, hwaddr addr,
DPRINTF("%s: cpu %d addr " TARGET_FMT_plx " <= %08x\n", __func__, idx,
addr, val);
+
+ if (idx < 0) {
+ return;
+ }
+
if (addr & 0xF)
return;
dst = &opp->dst[idx];
@@ -875,6 +884,11 @@ static uint32_t openpic_cpu_read_internal(void *opaque, hwaddr addr,
DPRINTF("%s: cpu %d addr " TARGET_FMT_plx "\n", __func__, idx, addr);
retval = 0xFFFFFFFF;
+
+ if (idx < 0) {
+ return retval;
+ }
+
if (addr & 0xF)
return retval;
dst = &opp->dst[idx];