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authorPeter Maydell <peter.maydell@linaro.org>2019-09-04 10:16:00 +0100
committerPeter Maydell <peter.maydell@linaro.org>2019-09-04 10:16:00 +0100
commit379d83f2c92879f4418aa9c57fd1fcbc3c82d384 (patch)
treeba5f251e156c27703fbc09f1e4f4a8808f58399f
parent03a6190518206175f280704430811919211ce96a (diff)
parentabd4393d769d9fe2333b2e83e00f911a78475943 (diff)
Merge remote-tracking branch 'remotes/amarkovic/tags/mips-queue-aug-29-2019' into staging
MIPS queue for August 29th, 2019 # gpg: Signature made Thu 29 Aug 2019 11:19:28 BST # gpg: using RSA key D4972A8967F75A65 # gpg: Good signature from "Aleksandar Markovic <amarkovic@wavecomp.com>" [unknown] # gpg: WARNING: This key is not certified with a trusted signature! # gpg: There is no indication that the signature belongs to the owner. # Primary key fingerprint: 8526 FBF1 5DA3 811F 4A01 DD75 D497 2A89 67F7 5A65 * remotes/amarkovic/tags/mips-queue-aug-29-2019: (31 commits) target/mips: Fix emulation of ST.W in system mode target/mips: Clean up handling of CP0 register 31 target/mips: Clean up handling of CP0 register 30 target/mips: Clean up handling of CP0 register 29 target/mips: Clean up handling of CP0 register 28 target/mips: Clean up handling of CP0 register 27 target/mips: Clean up handling of CP0 register 26 target/mips: Clean up handling of CP0 register 25 target/mips: Clean up handling of CP0 register 24 target/mips: Clean up handling of CP0 register 23 target/mips: Clean up handling of CP0 register 20 target/mips: Clean up handling of CP0 register 19 target/mips: Clean up handling of CP0 register 18 target/mips: Clean up handling of CP0 register 17 target/mips: Clean up handling of CP0 register 16 target/mips: Clean up handling of CP0 register 15 target/mips: Clean up handling of CP0 register 14 target/mips: Clean up handling of CP0 register 13 target/mips: Clean up handling of CP0 register 12 target/mips: Clean up handling of CP0 register 11 ... Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Diffstat
-rw-r--r--target/mips/cpu.h113
-rw-r--r--target/mips/op_helper.c16
-rw-r--r--target/mips/translate.c1142
3 files changed, 685 insertions, 586 deletions
diff --git a/target/mips/cpu.h b/target/mips/cpu.h
index 1fd4a180e1..ca00f41daf 100644
--- a/target/mips/cpu.h
+++ b/target/mips/cpu.h
@@ -192,14 +192,14 @@ typedef struct mips_def_t mips_def_t;
* Register 16 Register 17 Register 18 Register 19
* ----------- ----------- ----------- -----------
*
- * 0 Config LLAddr WatchLo WatchHi
- * 1 Config1 MAAR WatchLo WatchHi
- * 2 Config2 MAARI WatchLo WatchHi
- * 3 Config3 WatchLo WatchHi
- * 4 Config4 WatchLo WatchHi
- * 5 Config5 WatchLo WatchHi
- * 6 WatchLo WatchHi
- * 7 WatchLo WatchHi
+ * 0 Config LLAddr WatchLo0 WatchHi
+ * 1 Config1 MAAR WatchLo1 WatchHi
+ * 2 Config2 MAARI WatchLo2 WatchHi
+ * 3 Config3 WatchLo3 WatchHi
+ * 4 Config4 WatchLo4 WatchHi
+ * 5 Config5 WatchLo5 WatchHi
+ * 6 WatchLo6 WatchHi
+ * 7 WatchLo7 WatchHi
*
*
* Register 20 Register 21 Register 22 Register 23
@@ -233,12 +233,12 @@ typedef struct mips_def_t mips_def_t;
*
* 0 DataLo DataHi ErrorEPC DESAVE
* 1 TagLo TagHi
- * 2 DataLo DataHi KScratch<n>
- * 3 TagLo TagHi KScratch<n>
- * 4 DataLo DataHi KScratch<n>
- * 5 TagLo TagHi KScratch<n>
- * 6 DataLo DataHi KScratch<n>
- * 7 TagLo TagHi KScratch<n>
+ * 2 DataLo1 DataHi1 KScratch<n>
+ * 3 TagLo1 TagHi1 KScratch<n>
+ * 4 DataLo2 DataHi2 KScratch<n>
+ * 5 TagLo2 TagHi2 KScratch<n>
+ * 6 DataLo3 DataHi3 KScratch<n>
+ * 7 TagLo3 TagHi3 KScratch<n>
*
*/
#define CP0_REGISTER_00 0
@@ -277,29 +277,63 @@ typedef struct mips_def_t mips_def_t;
/* CP0 Register 00 */
#define CP0_REG00__INDEX 0
+#define CP0_REG00__MVPCONTROL 1
+#define CP0_REG00__MVPCONF0 2
+#define CP0_REG00__MVPCONF1 3
#define CP0_REG00__VPCONTROL 4
/* CP0 Register 01 */
+#define CP0_REG01__RANDOM 0
+#define CP0_REG01__VPECONTROL 1
+#define CP0_REG01__VPECONF0 2
+#define CP0_REG01__VPECONF1 3
+#define CP0_REG01__YQMASK 4
+#define CP0_REG01__VPESCHEDULE 5
+#define CP0_REG01__VPESCHEFBACK 6
+#define CP0_REG01__VPEOPT 7
/* CP0 Register 02 */
#define CP0_REG02__ENTRYLO0 0
+#define CP0_REG02__TCSTATUS 1
+#define CP0_REG02__TCBIND 2
+#define CP0_REG02__TCRESTART 3
+#define CP0_REG02__TCHALT 4
+#define CP0_REG02__TCCONTEXT 5
+#define CP0_REG02__TCSCHEDULE 6
+#define CP0_REG02__TCSCHEFBACK 7
/* CP0 Register 03 */
#define CP0_REG03__ENTRYLO1 0
#define CP0_REG03__GLOBALNUM 1
+#define CP0_REG03__TCOPT 7
/* CP0 Register 04 */
#define CP0_REG04__CONTEXT 0
+#define CP0_REG04__CONTEXTCONFIG 1
#define CP0_REG04__USERLOCAL 2
+#define CP0_REG04__XCONTEXTCONFIG 3
#define CP0_REG04__DBGCONTEXTID 4
#define CP0_REG00__MMID 5
/* CP0 Register 05 */
#define CP0_REG05__PAGEMASK 0
#define CP0_REG05__PAGEGRAIN 1
+#define CP0_REG05__SEGCTL0 2
+#define CP0_REG05__SEGCTL1 3
+#define CP0_REG05__SEGCTL2 4
+#define CP0_REG05__PWBASE 5
+#define CP0_REG05__PWFIELD 6
+#define CP0_REG05__PWSIZE 7
/* CP0 Register 06 */
#define CP0_REG06__WIRED 0
+#define CP0_REG06__SRSCONF0 1
+#define CP0_REG06__SRSCONF1 2
+#define CP0_REG06__SRSCONF2 3
+#define CP0_REG06__SRSCONF3 4
+#define CP0_REG06__SRSCONF4 5
+#define CP0_REG06__PWCTL 6
/* CP0 Register 07 */
#define CP0_REG07__HWRENA 0
/* CP0 Register 08 */
#define CP0_REG08__BADVADDR 0
#define CP0_REG08__BADINSTR 1
#define CP0_REG08__BADINSTRP 2
+#define CP0_REG08__BADINSTRX 3
/* CP0 Register 09 */
#define CP0_REG09__COUNT 0
#define CP0_REG09__SAARI 6
@@ -308,6 +342,7 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG10__ENTRYHI 0
#define CP0_REG10__GUESTCTL1 4
#define CP0_REG10__GUESTCTL2 5
+#define CP0_REG10__GUESTCTL3 6
/* CP0 Register 11 */
#define CP0_REG11__COMPARE 0
#define CP0_REG11__GUESTCTL0EXT 4
@@ -315,17 +350,24 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG12__STATUS 0
#define CP0_REG12__INTCTL 1
#define CP0_REG12__SRSCTL 2
+#define CP0_REG12__SRSMAP 3
+#define CP0_REG12__VIEW_IPL 4
+#define CP0_REG12__SRSMAP2 5
#define CP0_REG12__GUESTCTL0 6
#define CP0_REG12__GTOFFSET 7
/* CP0 Register 13 */
#define CP0_REG13__CAUSE 0
+#define CP0_REG13__VIEW_RIPL 4
+#define CP0_REG13__NESTEDEXC 5
/* CP0 Register 14 */
#define CP0_REG14__EPC 0
+#define CP0_REG14__NESTEDEPC 2
/* CP0 Register 15 */
#define CP0_REG15__PRID 0
#define CP0_REG15__EBASE 1
#define CP0_REG15__CDMMBASE 2
#define CP0_REG15__CMGCRBASE 3
+#define CP0_REG15__BEVVA 4
/* CP0 Register 16 */
#define CP0_REG16__CONFIG 0
#define CP0_REG16__CONFIG1 1
@@ -333,7 +375,8 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG16__CONFIG3 3
#define CP0_REG16__CONFIG4 4
#define CP0_REG16__CONFIG5 5
-#define CP0_REG00__CONFIG7 7
+#define CP0_REG16__CONFIG6 6
+#define CP0_REG16__CONFIG7 7
/* CP0 Register 17 */
#define CP0_REG17__LLADDR 0
#define CP0_REG17__MAAR 1
@@ -343,17 +386,31 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG18__WATCHLO1 1
#define CP0_REG18__WATCHLO2 2
#define CP0_REG18__WATCHLO3 3
+#define CP0_REG18__WATCHLO4 4
+#define CP0_REG18__WATCHLO5 5
+#define CP0_REG18__WATCHLO6 6
+#define CP0_REG18__WATCHLO7 7
/* CP0 Register 19 */
#define CP0_REG19__WATCHHI0 0
#define CP0_REG19__WATCHHI1 1
#define CP0_REG19__WATCHHI2 2
#define CP0_REG19__WATCHHI3 3
+#define CP0_REG19__WATCHHI4 4
+#define CP0_REG19__WATCHHI5 5
+#define CP0_REG19__WATCHHI6 6
+#define CP0_REG19__WATCHHI7 7
/* CP0 Register 20 */
#define CP0_REG20__XCONTEXT 0
/* CP0 Register 21 */
/* CP0 Register 22 */
/* CP0 Register 23 */
#define CP0_REG23__DEBUG 0
+#define CP0_REG23__TRACECONTROL 1
+#define CP0_REG23__TRACECONTROL2 2
+#define CP0_REG23__USERTRACEDATA1 3
+#define CP0_REG23__TRACEIBPC 4
+#define CP0_REG23__TRACEDBPC 5
+#define CP0_REG23__DEBUG2 6
/* CP0 Register 24 */
#define CP0_REG24__DEPC 0
/* CP0 Register 25 */
@@ -366,17 +423,27 @@ typedef struct mips_def_t mips_def_t;
#define CP0_REG25__PERFCTL3 6
#define CP0_REG25__PERFCNT3 7
/* CP0 Register 26 */
-#define CP0_REG00__ERRCTL 0
+#define CP0_REG26__ERRCTL 0
/* CP0 Register 27 */
#define CP0_REG27__CACHERR 0
/* CP0 Register 28 */
-#define CP0_REG28__ITAGLO 0
-#define CP0_REG28__IDATALO 1
-#define CP0_REG28__DTAGLO 2
-#define CP0_REG28__DDATALO 3
+#define CP0_REG28__TAGLO 0
+#define CP0_REG28__DATALO 1
+#define CP0_REG28__TAGLO1 2
+#define CP0_REG28__DATALO1 3
+#define CP0_REG28__TAGLO2 4
+#define CP0_REG28__DATALO2 5
+#define CP0_REG28__TAGLO3 6
+#define CP0_REG28__DATALO3 7
/* CP0 Register 29 */
-#define CP0_REG29__IDATAHI 1
-#define CP0_REG29__DDATAHI 3
+#define CP0_REG29__TAGHI 0
+#define CP0_REG29__DATAHI 1
+#define CP0_REG29__TAGHI1 2
+#define CP0_REG29__DATAHI1 3
+#define CP0_REG29__TAGHI2 4
+#define CP0_REG29__DATAHI2 5
+#define CP0_REG29__TAGHI3 6
+#define CP0_REG29__DATAHI3 7
/* CP0 Register 30 */
#define CP0_REG30__ERROREPC 0
/* CP0 Register 31 */
@@ -546,7 +613,6 @@ struct CPUMIPSState {
* CP0 Register 4
*/
target_ulong CP0_Context;
- target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
int32_t CP0_MemoryMapID;
/*
* CP0 Register 5
@@ -957,6 +1023,7 @@ struct CPUMIPSState {
* CP0 Register 31
*/
int32_t CP0_DESAVE;
+ target_ulong CP0_KScratch[MIPS_KSCRATCH_NUM];
/* We waste some space so we can handle shadow registers like TCs. */
TCState tcs[MIPS_SHADOW_SET_MAX];
diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c
index f88a3ab904..5b8bb203f0 100644
--- a/target/mips/op_helper.c
+++ b/target/mips/op_helper.c
@@ -4692,15 +4692,15 @@ void helper_msa_st_w(CPUMIPSState *env, uint32_t wd,
ensure_writable_pages(env, addr, mmu_idx, GETPC());
#if !defined(CONFIG_USER_ONLY)
#if !defined(HOST_WORDS_BIGENDIAN)
- helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[0]);
- helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[1]);
- helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[2]);
- helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[3]);
+ helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[0], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[1], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[2], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[3], oi, GETPC());
#else
- helper_ret_stl_mmu(env, addr + (1 << DF_WORD), oi, GETPC(), pwd->w[0]);
- helper_ret_stl_mmu(env, addr + (0 << DF_WORD), oi, GETPC(), pwd->w[1]);
- helper_ret_stl_mmu(env, addr + (3 << DF_WORD), oi, GETPC(), pwd->w[2]);
- helper_ret_stl_mmu(env, addr + (2 << DF_WORD), oi, GETPC(), pwd->w[3]);
+ helper_ret_stl_mmu(env, addr + (1 << DF_WORD), pwd->w[0], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (0 << DF_WORD), pwd->w[1], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (3 << DF_WORD), pwd->w[2], oi, GETPC());
+ helper_ret_stl_mmu(env, addr + (2 << DF_WORD), pwd->w[3], oi, GETPC());
#endif
#else
#if !defined(HOST_WORDS_BIGENDIAN)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 8ebde6ffee..f6d14245f1 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -6647,7 +6647,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
gen_mfhc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
register_name = "EntryLo1";
@@ -6658,7 +6658,7 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mfhc0_saar(arg, cpu_env);
register_name = "SAAR";
@@ -6669,12 +6669,12 @@ static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_mfhc0_load64(arg, offsetof(CPUMIPSState, CP0_LLAddr),
ctx->CP0_LLAddr_shift);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mfhc0_maar(arg, cpu_env);
register_name = "MAAR";
@@ -6728,7 +6728,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
CP0_CHECK(ctx->hflags & MIPS_HFLAG_ELPA);
tcg_gen_andi_tl(arg, arg, mask);
gen_mthc0_entrylo(arg, offsetof(CPUMIPSState, CP0_EntryLo1));
@@ -6740,7 +6740,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mthc0_saar(cpu_env, arg);
register_name = "SAAR";
@@ -6751,7 +6751,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
/*
* LLAddr is read-only (the only exception is bit 0 if LLB is
* supported); the CP0_LLAddr_rw_bitmask does not seem to be
@@ -6760,7 +6760,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel)
*/
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mthc0_maar(cpu_env, arg);
register_name = "MAAR";
@@ -6813,26 +6813,26 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(arg, cpu_env);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(arg, cpu_env);
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(arg, cpu_env);
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
register_name = "VPControl";
@@ -6843,42 +6843,42 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
- case 0:
+ case CP0_REG01__RANDOM:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
gen_helper_mfc0_random(arg, cpu_env);
register_name = "Random";
break;
- case 1:
+ case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
register_name = "VPEControl";
break;
- case 2:
+ case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
register_name = "VPEConf0";
break;
- case 3:
+ case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
register_name = "VPEConf1";
break;
- case 4:
+ case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_YQMask));
register_name = "YQMask";
break;
- case 5:
+ case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
- case 6:
+ case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
- case 7:
+ case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
register_name = "VPEOpt";
@@ -6889,7 +6889,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env,
@@ -6906,37 +6906,37 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(arg, cpu_env);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(arg, cpu_env);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcrestart(arg, cpu_env);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tchalt(arg, cpu_env);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tccontext(arg, cpu_env);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschedule(arg, cpu_env);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcschefback(arg, cpu_env);
register_name = "TCScheFBack";
@@ -6947,7 +6947,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env,
@@ -6964,7 +6964,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
register_name = "EntryLo1";
break;
- case 1:
+ case CP0_REG03__GLOBALNUM:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
register_name = "GlobalNumber";
@@ -6975,16 +6975,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
- case 0:
+ case CP0_REG04__CONTEXT:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
tcg_gen_ext32s_tl(arg, arg);
register_name = "Context";
break;
- case 1:
- /* gen_helper_mfc0_contextconfig(arg); - SmartMIPS ASE */
+ case CP0_REG04__CONTEXTCONFIG:
+ /* SmartMIPS ASE */
+ /* gen_helper_mfc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
@@ -6997,44 +6998,44 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
- case 0:
+ case CP0_REG05__PAGEMASK:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
register_name = "PageMask";
break;
- case 1:
+ case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
- case 2:
+ case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl0";
break;
- case 3:
+ case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl1";
break;
- case 4:
+ case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
tcg_gen_ext32s_tl(arg, arg);
register_name = "SegCtl2";
break;
- case 5:
+ case CP0_REG05__PWBASE:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
- case 6:
+ case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWField));
register_name = "PWField";
break;
- case 7:
+ case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWSize));
register_name = "PWSize";
@@ -7045,36 +7046,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
- case 0:
+ case CP0_REG06__WIRED:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
register_name = "Wired";
break;
- case 1:
+ case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
- case 2:
+ case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1";
break;
- case 3:
+ case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2";
break;
- case 4:
+ case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3";
break;
- case 5:
+ case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4";
break;
- case 6:
+ case CP0_REG06__PWCTL:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
register_name = "PWCtl";
@@ -7085,7 +7086,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
- case 0:
+ case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna";
@@ -7096,22 +7097,22 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
- case 0:
+ case CP0_REG08__BADVADDR:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
tcg_gen_ext32s_tl(arg, arg);
register_name = "BadVAddr";
break;
- case 1:
+ case CP0_REG08__BADINSTR:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
register_name = "BadInstr";
break;
- case 2:
+ case CP0_REG08__BADINSTRP:
CP0_CHECK(ctx->bp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
register_name = "BadInstrP";
break;
- case 3:
+ case CP0_REG08__BADINSTRX:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
tcg_gen_andi_tl(arg, arg, ~0xffff);
@@ -7123,7 +7124,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 0:
+ case CP0_REG09__COUNT:
/* Mark as an IO operation because we read the time. */
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -7138,12 +7139,12 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Count";
break;
- case 6:
+ case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
register_name = "SAARI";
break;
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mfc0_saar(arg, cpu_env);
register_name = "SAAR";
@@ -7154,7 +7155,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
- case 0:
+ case CP0_REG10__ENTRYHI:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EntryHi";
@@ -7165,7 +7166,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
- case 0:
+ case CP0_REG11__COMPARE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
register_name = "Compare";
break;
@@ -7176,21 +7177,21 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
- case 0:
+ case CP0_REG12__STATUS:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
register_name = "Status";
break;
- case 1:
+ case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
- case 2:
+ case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
- case 3:
+ case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
@@ -7201,7 +7202,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
- case 0:
+ case CP0_REG13__CAUSE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
register_name = "Cause";
break;
@@ -7211,7 +7212,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
- case 0:
+ case CP0_REG14__EPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EPC";
@@ -7222,17 +7223,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
tcg_gen_ext32s_tl(arg, arg);
register_name = "EBase";
break;
- case 3:
+ case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@@ -7245,36 +7246,36 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
- case 0:
+ case CP0_REG16__CONFIG:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
register_name = "Config";
break;
- case 1:
+ case CP0_REG16__CONFIG1:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
register_name = "Config1";
break;
- case 2:
+ case CP0_REG16__CONFIG2:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
register_name = "Config2";
break;
- case 3:
+ case CP0_REG16__CONFIG3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
register_name = "Config3";
break;
- case 4:
+ case CP0_REG16__CONFIG4:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
register_name = "Config4";
break;
- case 5:
+ case CP0_REG16__CONFIG5:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
register_name = "Config5";
break;
/* 6,7 are implementation dependent */
- case 6:
+ case CP0_REG16__CONFIG6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
register_name = "Config6";
break;
- case 7:
+ case CP0_REG16__CONFIG7:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
register_name = "Config7";
break;
@@ -7284,16 +7285,16 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_mfc0_lladdr(arg, cpu_env);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mfc0_maar(arg, cpu_env);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
register_name = "MAARI";
@@ -7304,14 +7305,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG18__WATCHLO0:
+ case CP0_REG18__WATCHLO1:
+ case CP0_REG18__WATCHLO2:
+ case CP0_REG18__WATCHLO3:
+ case CP0_REG18__WATCHLO4:
+ case CP0_REG18__WATCHLO5:
+ case CP0_REG18__WATCHLO6:
+ case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -7322,14 +7323,14 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG19__WATCHHI0:
+ case CP0_REG19__WATCHHI1:
+ case CP0_REG19__WATCHHI2:
+ case CP0_REG19__WATCHHI3:
+ case CP0_REG19__WATCHHI4:
+ case CP0_REG19__WATCHHI5:
+ case CP0_REG19__WATCHHI6:
+ case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
register_name = "WatchHi";
@@ -7340,7 +7341,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
- case 0:
+ case CP0_REG20__XCONTEXT:
#if defined(TARGET_MIPS64)
check_insn(ctx, ISA_MIPS3);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
@@ -7370,25 +7371,34 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_23:
switch (sel) {
- case 0:
+ case CP0_REG23__DEBUG:
gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
register_name = "Debug";
break;
- case 1:
-// gen_helper_mfc0_tracecontrol(arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL:
+ /* PDtrace support */
+ /* gen_helper_mfc0_tracecontrol(arg); */
register_name = "TraceControl";
goto cp0_unimplemented;
- case 2:
-// gen_helper_mfc0_tracecontrol2(arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL2:
+ /* PDtrace support */
+ /* gen_helper_mfc0_tracecontrol2(arg); */
register_name = "TraceControl2";
goto cp0_unimplemented;
- case 3:
-// gen_helper_mfc0_usertracedata(arg); /* PDtrace support */
- register_name = "UserTraceData";
+ case CP0_REG23__USERTRACEDATA1:
+ /* PDtrace support */
+ /* gen_helper_mfc0_usertracedata1(arg);*/
+ register_name = "UserTraceData1";
goto cp0_unimplemented;
- case 4:
-// gen_helper_mfc0_tracebpc(arg); /* PDtrace support */
- register_name = "TraceBPC";
+ case CP0_REG23__TRACEIBPC:
+ /* PDtrace support */
+ /* gen_helper_mfc0_traceibpc(arg); */
+ register_name = "TraceIBPC";
+ goto cp0_unimplemented;
+ case CP0_REG23__TRACEDBPC:
+ /* PDtrace support */
+ /* gen_helper_mfc0_tracedbpc(arg); */
+ register_name = "TraceDBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -7396,7 +7406,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
- case 0:
+ case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
tcg_gen_ext32s_tl(arg, arg);
@@ -7408,35 +7418,35 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
- case 0:
+ case CP0_REG25__PERFCTL0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
register_name = "Performance0";
break;
- case 1:
+ case CP0_REG25__PERFCNT0:
/* gen_helper_mfc0_performance1(arg); */
register_name = "Performance1";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG25__PERFCTL1:
/* gen_helper_mfc0_performance2(arg); */
register_name = "Performance2";
goto cp0_unimplemented;
- case 3:
+ case CP0_REG25__PERFCNT1:
/* gen_helper_mfc0_performance3(arg); */
register_name = "Performance3";
goto cp0_unimplemented;
- case 4:
+ case CP0_REG25__PERFCTL2:
/* gen_helper_mfc0_performance4(arg); */
register_name = "Performance4";
goto cp0_unimplemented;
- case 5:
+ case CP0_REG25__PERFCNT2:
/* gen_helper_mfc0_performance5(arg); */
register_name = "Performance5";
goto cp0_unimplemented;
- case 6:
+ case CP0_REG25__PERFCTL3:
/* gen_helper_mfc0_performance6(arg); */
register_name = "Performance6";
goto cp0_unimplemented;
- case 7:
+ case CP0_REG25__PERFCNT3:
/* gen_helper_mfc0_performance7(arg); */
register_name = "Performance7";
goto cp0_unimplemented;
@@ -7446,7 +7456,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
- case 0:
+ case CP0_REG26__ERRCTL:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
register_name = "ErrCtl";
break;
@@ -7456,10 +7466,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
+ case CP0_REG27__CACHERR:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
register_name = "CacheErr";
break;
@@ -7469,10 +7476,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG28__TAGLO:
+ case CP0_REG28__TAGLO1:
+ case CP0_REG28__TAGLO2:
+ case CP0_REG28__TAGLO3:
{
TCGv_i64 tmp = tcg_temp_new_i64();
tcg_gen_ld_i64(tmp, cpu_env, offsetof(CPUMIPSState, CP0_TagLo));
@@ -7481,10 +7488,10 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
}
register_name = "TagLo";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG28__DATALO:
+ case CP0_REG28__DATALO1:
+ case CP0_REG28__DATALO2:
+ case CP0_REG28__DATALO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
register_name = "DataLo";
break;
@@ -7494,17 +7501,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG29__TAGHI:
+ case CP0_REG29__TAGHI1:
+ case CP0_REG29__TAGHI2:
+ case CP0_REG29__TAGHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
register_name = "TagHi";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG29__DATAHI:
+ case CP0_REG29__DATAHI1:
+ case CP0_REG29__DATAHI2:
+ case CP0_REG29__DATAHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
register_name = "DataHi";
break;
@@ -7514,7 +7521,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_30:
switch (sel) {
- case 0:
+ case CP0_REG30__ERROREPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
tcg_gen_ext32s_tl(arg, arg);
register_name = "ErrorEPC";
@@ -7525,17 +7532,17 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
- case 0:
+ case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG31__KSCRATCH1:
+ case CP0_REG31__KSCRATCH2:
+ case CP0_REG31__KSCRATCH3:
+ case CP0_REG31__KSCRATCH4:
+ case CP0_REG31__KSCRATCH5:
+ case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -7573,26 +7580,26 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_helper_mtc0_index(cpu_env, arg);
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(cpu_env, arg);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "VPControl";
@@ -7603,43 +7610,43 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
- case 0:
+ case CP0_REG01__RANDOM:
/* ignored */
register_name = "Random";
break;
- case 1:
+ case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpecontrol(cpu_env, arg);
register_name = "VPEControl";
break;
- case 2:
+ case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf0(cpu_env, arg);
register_name = "VPEConf0";
break;
- case 3:
+ case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf1(cpu_env, arg);
register_name = "VPEConf1";
break;
- case 4:
+ case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_yqmask(cpu_env, arg);
register_name = "YQMask";
break;
- case 5:
+ case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
- case 6:
+ case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
- case 7:
+ case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeopt(cpu_env, arg);
register_name = "VPEOpt";
@@ -7650,41 +7657,41 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
gen_helper_mtc0_entrylo0(cpu_env, arg);
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(cpu_env, arg);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(cpu_env, arg);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(cpu_env, arg);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(cpu_env, arg);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(cpu_env, arg);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(cpu_env, arg);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(cpu_env, arg);
register_name = "TCScheFBack";
@@ -7695,11 +7702,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
gen_helper_mtc0_entrylo1(cpu_env, arg);
register_name = "EntryLo1";
break;
- case 1:
+ case CP0_REG03__GLOBALNUM:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "GlobalNumber";
@@ -7710,15 +7717,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
- case 0:
+ case CP0_REG04__CONTEXT:
gen_helper_mtc0_context(cpu_env, arg);
register_name = "Context";
break;
- case 1:
-// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
+ case CP0_REG04__CONTEXTCONFIG:
+ /* SmartMIPS ASE */
+ /* gen_helper_mtc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
@@ -7730,42 +7738,42 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
- case 0:
+ case CP0_REG05__PAGEMASK:
gen_helper_mtc0_pagemask(cpu_env, arg);
register_name = "PageMask";
break;
- case 1:
+ case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain";
ctx->base.is_jmp = DISAS_STOP;
break;
- case 2:
+ case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl0(cpu_env, arg);
register_name = "SegCtl0";
break;
- case 3:
+ case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl1(cpu_env, arg);
register_name = "SegCtl1";
break;
- case 4:
+ case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl2(cpu_env, arg);
register_name = "SegCtl2";
break;
- case 5:
+ case CP0_REG05__PWBASE:
check_pw(ctx);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
- case 6:
+ case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_helper_mtc0_pwfield(cpu_env, arg);
register_name = "PWField";
break;
- case 7:
+ case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_helper_mtc0_pwsize(cpu_env, arg);
register_name = "PWSize";
@@ -7776,36 +7784,36 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
- case 0:
+ case CP0_REG06__WIRED:
gen_helper_mtc0_wired(cpu_env, arg);
register_name = "Wired";
break;
- case 1:
+ case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0";
break;
- case 2:
+ case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1";
break;
- case 3:
+ case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2";
break;
- case 4:
+ case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3";
break;
- case 5:
+ case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4";
break;
- case 6:
+ case CP0_REG06__PWCTL:
check_pw(ctx);
gen_helper_mtc0_pwctl(cpu_env, arg);
register_name = "PWCtl";
@@ -7816,7 +7824,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
- case 0:
+ case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
@@ -7828,19 +7836,19 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
- case 0:
+ case CP0_REG08__BADVADDR:
/* ignored */
register_name = "BadVAddr";
break;
- case 1:
+ case CP0_REG08__BADINSTR:
/* ignored */
register_name = "BadInstr";
break;
- case 2:
+ case CP0_REG08__BADINSTRP:
/* ignored */
register_name = "BadInstrP";
break;
- case 3:
+ case CP0_REG08__BADINSTRX:
/* ignored */
register_name = "BadInstrX";
break;
@@ -7850,16 +7858,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 0:
+ case CP0_REG09__COUNT:
gen_helper_mtc0_count(cpu_env, arg);
register_name = "Count";
break;
- case 6:
+ case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saari(cpu_env, arg);
register_name = "SAARI";
break;
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saar(cpu_env, arg);
register_name = "SAAR";
@@ -7870,7 +7878,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
- case 0:
+ case CP0_REG10__ENTRYHI:
gen_helper_mtc0_entryhi(cpu_env, arg);
register_name = "EntryHi";
break;
@@ -7880,7 +7888,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
- case 0:
+ case CP0_REG11__COMPARE:
gen_helper_mtc0_compare(cpu_env, arg);
register_name = "Compare";
break;
@@ -7891,7 +7899,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
- case 0:
+ case CP0_REG12__STATUS:
save_cpu_state(ctx, 1);
gen_helper_mtc0_status(cpu_env, arg);
/* DISAS_STOP isn't good enough here, hflags may have changed. */
@@ -7899,21 +7907,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Status";
break;
- case 1:
+ case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
- case 2:
+ case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
break;
- case 3:
+ case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
@@ -7926,7 +7934,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
- case 0:
+ case CP0_REG13__CAUSE:
save_cpu_state(ctx, 1);
gen_helper_mtc0_cause(cpu_env, arg);
/*
@@ -7944,7 +7952,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
- case 0:
+ case CP0_REG14__EPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
@@ -7954,11 +7962,11 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
@@ -7969,45 +7977,45 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
- case 0:
+ case CP0_REG16__CONFIG:
gen_helper_mtc0_config0(cpu_env, arg);
register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 1:
+ case CP0_REG16__CONFIG1:
/* ignored, read only */
register_name = "Config1";
break;
- case 2:
+ case CP0_REG16__CONFIG2:
gen_helper_mtc0_config2(cpu_env, arg);
register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 3:
+ case CP0_REG16__CONFIG3:
gen_helper_mtc0_config3(cpu_env, arg);
register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 4:
+ case CP0_REG16__CONFIG4:
gen_helper_mtc0_config4(cpu_env, arg);
register_name = "Config4";
ctx->base.is_jmp = DISAS_STOP;
break;
- case 5:
+ case CP0_REG16__CONFIG5:
gen_helper_mtc0_config5(cpu_env, arg);
register_name = "Config5";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
/* 6,7 are implementation dependent */
- case 6:
+ case CP0_REG16__CONFIG6:
/* ignored */
register_name = "Config6";
break;
- case 7:
+ case CP0_REG16__CONFIG7:
/* ignored */
register_name = "Config7";
break;
@@ -8018,16 +8026,16 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_mtc0_lladdr(cpu_env, arg);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maar(cpu_env, arg);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maari(cpu_env, arg);
register_name = "MAARI";
@@ -8038,14 +8046,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG18__WATCHLO0:
+ case CP0_REG18__WATCHLO1:
+ case CP0_REG18__WATCHLO2:
+ case CP0_REG18__WATCHLO3:
+ case CP0_REG18__WATCHLO4:
+ case CP0_REG18__WATCHLO5:
+ case CP0_REG18__WATCHLO6:
+ case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -8056,14 +8064,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG19__WATCHHI0:
+ case CP0_REG19__WATCHHI1:
+ case CP0_REG19__WATCHHI2:
+ case CP0_REG19__WATCHHI3:
+ case CP0_REG19__WATCHHI4:
+ case CP0_REG19__WATCHHI5:
+ case CP0_REG19__WATCHHI6:
+ case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
register_name = "WatchHi";
@@ -8074,7 +8082,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
- case 0:
+ case CP0_REG20__XCONTEXT:
#if defined(TARGET_MIPS64)
check_insn(ctx, ISA_MIPS3);
gen_helper_mtc0_xcontext(cpu_env, arg);
@@ -8103,38 +8111,49 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_23:
switch (sel) {
- case 0:
+ case CP0_REG23__DEBUG:
gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Debug";
break;
- case 1:
-// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
register_name = "TraceControl";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
- case 2:
-// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL2:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
register_name = "TraceControl2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
- case 3:
+ case CP0_REG23__USERTRACEDATA1:
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
-// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
+ /* PDtrace support */
+ /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
register_name = "UserTraceData";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
goto cp0_unimplemented;
- case 4:
-// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACEIBPC:
+ /* PDtrace support */
+ /* gen_helper_mtc0_traceibpc(cpu_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- register_name = "TraceBPC";
+ register_name = "TraceIBPC";
+ goto cp0_unimplemented;
+ case CP0_REG23__TRACEDBPC:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */
+ /* Stop translation as we may have switched the execution mode */
+ ctx->base.is_jmp = DISAS_STOP;
+ register_name = "TraceDBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -8142,7 +8161,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
- case 0:
+ case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
@@ -8153,35 +8172,35 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
- case 0:
+ case CP0_REG25__PERFCTL0:
gen_helper_mtc0_performance0(cpu_env, arg);
register_name = "Performance0";
break;
- case 1:
+ case CP0_REG25__PERFCNT0:
/* gen_helper_mtc0_performance1(arg); */
register_name = "Performance1";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG25__PERFCTL1:
/* gen_helper_mtc0_performance2(arg); */
register_name = "Performance2";
goto cp0_unimplemented;
- case 3:
+ case CP0_REG25__PERFCNT1:
/* gen_helper_mtc0_performance3(arg); */
register_name = "Performance3";
goto cp0_unimplemented;
- case 4:
+ case CP0_REG25__PERFCTL2:
/* gen_helper_mtc0_performance4(arg); */
register_name = "Performance4";
goto cp0_unimplemented;
- case 5:
+ case CP0_REG25__PERFCNT2:
/* gen_helper_mtc0_performance5(arg); */
register_name = "Performance5";
goto cp0_unimplemented;
- case 6:
+ case CP0_REG25__PERFCTL3:
/* gen_helper_mtc0_performance6(arg); */
register_name = "Performance6";
goto cp0_unimplemented;
- case 7:
+ case CP0_REG25__PERFCNT3:
/* gen_helper_mtc0_performance7(arg); */
register_name = "Performance7";
goto cp0_unimplemented;
@@ -8191,7 +8210,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
- case 0:
+ case CP0_REG26__ERRCTL:
gen_helper_mtc0_errctl(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "ErrCtl";
@@ -8202,10 +8221,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
+ case CP0_REG27__CACHERR:
/* ignored */
register_name = "CacheErr";
break;
@@ -8215,17 +8231,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG28__TAGLO:
+ case CP0_REG28__TAGLO1:
+ case CP0_REG28__TAGLO2:
+ case CP0_REG28__TAGLO3:
gen_helper_mtc0_taglo(cpu_env, arg);
register_name = "TagLo";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG28__DATALO:
+ case CP0_REG28__DATALO1:
+ case CP0_REG28__DATALO2:
+ case CP0_REG28__DATALO3:
gen_helper_mtc0_datalo(cpu_env, arg);
register_name = "DataLo";
break;
@@ -8235,17 +8251,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG29__TAGHI:
+ case CP0_REG29__TAGHI1:
+ case CP0_REG29__TAGHI2:
+ case CP0_REG29__TAGHI3:
gen_helper_mtc0_taghi(cpu_env, arg);
register_name = "TagHi";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG29__DATAHI:
+ case CP0_REG29__DATAHI1:
+ case CP0_REG29__DATAHI2:
+ case CP0_REG29__DATAHI3:
gen_helper_mtc0_datahi(cpu_env, arg);
register_name = "DataHi";
break;
@@ -8256,7 +8272,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_30:
switch (sel) {
- case 0:
+ case CP0_REG30__ERROREPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
@@ -8266,17 +8282,17 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
- case 0:
+ case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG31__KSCRATCH1:
+ case CP0_REG31__KSCRATCH2:
+ case CP0_REG31__KSCRATCH3:
+ case CP0_REG31__KSCRATCH4:
+ case CP0_REG31__KSCRATCH5:
+ case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -8319,26 +8335,26 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Index));
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpcontrol(arg, cpu_env);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf0(arg, cpu_env);
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_mvpconf1(arg, cpu_env);
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPControl));
register_name = "VPControl";
@@ -8349,42 +8365,42 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
- case 0:
+ case CP0_REG01__RANDOM:
CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
gen_helper_mfc0_random(arg, cpu_env);
register_name = "Random";
break;
- case 1:
+ case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEControl));
register_name = "VPEControl";
break;
- case 2:
+ case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf0));
register_name = "VPEConf0";
break;
- case 3:
+ case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEConf1));
register_name = "VPEConf1";
break;
- case 4:
+ case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
register_name = "YQMask";
break;
- case 5:
+ case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
- case 6:
+ case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
- case 7:
+ case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_VPEOpt));
register_name = "VPEOpt";
@@ -8395,41 +8411,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcstatus(arg, cpu_env);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mfc0_tcbind(arg, cpu_env);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcrestart(arg, cpu_env);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tchalt(arg, cpu_env);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tccontext(arg, cpu_env);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcschedule(arg, cpu_env);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_dmfc0_tcschefback(arg, cpu_env);
register_name = "TCScheFBack";
@@ -8440,11 +8456,11 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo1));
register_name = "EntryLo1";
break;
- case 1:
+ case CP0_REG03__GLOBALNUM:
CP0_CHECK(ctx->vp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_GlobalNumber));
register_name = "GlobalNumber";
@@ -8455,15 +8471,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
- case 0:
+ case CP0_REG04__CONTEXT:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Context));
register_name = "Context";
break;
- case 1:
-// gen_helper_dmfc0_contextconfig(arg); /* SmartMIPS ASE */
+ case CP0_REG04__CONTEXTCONFIG:
+ /* SmartMIPS ASE */
+ /* gen_helper_dmfc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
@@ -8475,41 +8492,41 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
- case 0:
+ case CP0_REG05__PAGEMASK:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageMask));
register_name = "PageMask";
break;
- case 1:
+ case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PageGrain));
register_name = "PageGrain";
break;
- case 2:
+ case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl0));
register_name = "SegCtl0";
break;
- case 3:
+ case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl1));
register_name = "SegCtl1";
break;
- case 4:
+ case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_SegCtl2));
register_name = "SegCtl2";
break;
- case 5:
+ case CP0_REG05__PWBASE:
check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
- case 6:
+ case CP0_REG05__PWFIELD:
check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWField));
register_name = "PWField";
break;
- case 7:
+ case CP0_REG05__PWSIZE:
check_pw(ctx);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWSize));
register_name = "PWSize";
@@ -8520,36 +8537,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
- case 0:
+ case CP0_REG06__WIRED:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Wired));
register_name = "Wired";
break;
- case 1:
+ case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf0));
register_name = "SRSConf0";
break;
- case 2:
+ case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf1));
register_name = "SRSConf1";
break;
- case 3:
+ case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf2));
register_name = "SRSConf2";
break;
- case 4:
+ case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf3));
register_name = "SRSConf3";
break;
- case 5:
+ case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSConf4));
register_name = "SRSConf4";
break;
- case 6:
+ case CP0_REG06__PWCTL:
check_pw(ctx);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PWCtl));
register_name = "PWCtl";
@@ -8560,7 +8577,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
- case 0:
+ case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_HWREna));
register_name = "HWREna";
@@ -8571,21 +8588,21 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
- case 0:
+ case CP0_REG08__BADVADDR:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_BadVAddr));
register_name = "BadVAddr";
break;
- case 1:
+ case CP0_REG08__BADINSTR:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstr));
register_name = "BadInstr";
break;
- case 2:
+ case CP0_REG08__BADINSTRP:
CP0_CHECK(ctx->bp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrP));
register_name = "BadInstrP";
break;
- case 3:
+ case CP0_REG08__BADINSTRX:
CP0_CHECK(ctx->bi);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_BadInstrX));
tcg_gen_andi_tl(arg, arg, ~0xffff);
@@ -8597,7 +8614,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 0:
+ case CP0_REG09__COUNT:
/* Mark as an IO operation because we read the time. */
if (tb_cflags(ctx->base.tb) & CF_USE_ICOUNT) {
gen_io_start();
@@ -8612,12 +8629,12 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Count";
break;
- case 6:
+ case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SAARI));
register_name = "SAARI";
break;
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_dmfc0_saar(arg, cpu_env);
register_name = "SAAR";
@@ -8628,7 +8645,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
- case 0:
+ case CP0_REG10__ENTRYHI:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryHi));
register_name = "EntryHi";
break;
@@ -8638,7 +8655,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
- case 0:
+ case CP0_REG11__COMPARE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Compare));
register_name = "Compare";
break;
@@ -8649,21 +8666,21 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
- case 0:
+ case CP0_REG12__STATUS:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
register_name = "Status";
break;
- case 1:
+ case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
register_name = "IntCtl";
break;
- case 2:
+ case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
register_name = "SRSCtl";
break;
- case 3:
+ case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
register_name = "SRSMap";
@@ -8674,7 +8691,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
- case 0:
+ case CP0_REG13__CAUSE:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Cause));
register_name = "Cause";
break;
@@ -8684,7 +8701,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
- case 0:
+ case CP0_REG14__EPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
@@ -8694,16 +8711,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_PRid));
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EBase));
register_name = "EBase";
break;
- case 3:
+ case CP0_REG15__CMGCRBASE:
check_insn(ctx, ISA_MIPS32R2);
CP0_CHECK(ctx->cmgcr);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_CMGCRBase));
@@ -8715,36 +8732,36 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
- case 0:
+ case CP0_REG16__CONFIG:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config0));
register_name = "Config";
break;
- case 1:
+ case CP0_REG16__CONFIG1:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config1));
register_name = "Config1";
break;
- case 2:
+ case CP0_REG16__CONFIG2:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config2));
register_name = "Config2";
break;
- case 3:
+ case CP0_REG16__CONFIG3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config3));
register_name = "Config3";
break;
- case 4:
+ case CP0_REG16__CONFIG4:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config4));
register_name = "Config4";
break;
- case 5:
+ case CP0_REG16__CONFIG5:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
register_name = "Config5";
break;
/* 6,7 are implementation dependent */
- case 6:
+ case CP0_REG16__CONFIG6:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
register_name = "Config6";
break;
- case 7:
+ case CP0_REG16__CONFIG7:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config7));
register_name = "Config7";
break;
@@ -8754,16 +8771,16 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_dmfc0_lladdr(arg, cpu_env);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_dmfc0_maar(arg, cpu_env);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_MAARI));
register_name = "MAARI";
@@ -8774,14 +8791,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG18__WATCHLO0:
+ case CP0_REG18__WATCHLO1:
+ case CP0_REG18__WATCHLO2:
+ case CP0_REG18__WATCHLO3:
+ case CP0_REG18__WATCHLO4:
+ case CP0_REG18__WATCHLO5:
+ case CP0_REG18__WATCHLO6:
+ case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(dmfc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -8792,14 +8809,14 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG19__WATCHHI0:
+ case CP0_REG19__WATCHHI1:
+ case CP0_REG19__WATCHHI2:
+ case CP0_REG19__WATCHHI3:
+ case CP0_REG19__WATCHHI4:
+ case CP0_REG19__WATCHHI5:
+ case CP0_REG19__WATCHHI6:
+ case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(mfc0_watchhi, arg, sel);
register_name = "WatchHi";
@@ -8810,7 +8827,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
- case 0:
+ case CP0_REG20__XCONTEXT:
check_insn(ctx, ISA_MIPS3);
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_XContext));
register_name = "XContext";
@@ -8837,25 +8854,34 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_23:
switch (sel) {
- case 0:
+ case CP0_REG23__DEBUG:
gen_helper_mfc0_debug(arg, cpu_env); /* EJTAG support */
register_name = "Debug";
break;
- case 1:
-// gen_helper_dmfc0_tracecontrol(arg, cpu_env); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL:
+ /* PDtrace support */
+ /* gen_helper_dmfc0_tracecontrol(arg, cpu_env); */
register_name = "TraceControl";
goto cp0_unimplemented;
- case 2:
-// gen_helper_dmfc0_tracecontrol2(arg, cpu_env); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL2:
+ /* PDtrace support */
+ /* gen_helper_dmfc0_tracecontrol2(arg, cpu_env); */
register_name = "TraceControl2";
goto cp0_unimplemented;
- case 3:
-// gen_helper_dmfc0_usertracedata(arg, cpu_env); /* PDtrace support */
- register_name = "UserTraceData";
+ case CP0_REG23__USERTRACEDATA1:
+ /* PDtrace support */
+ /* gen_helper_dmfc0_usertracedata1(arg, cpu_env);*/
+ register_name = "UserTraceData1";
goto cp0_unimplemented;
- case 4:
-// gen_helper_dmfc0_tracebpc(arg, cpu_env); /* PDtrace support */
- register_name = "TraceBPC";
+ case CP0_REG23__TRACEIBPC:
+ /* PDtrace support */
+ /* gen_helper_dmfc0_traceibpc(arg, cpu_env); */
+ register_name = "TraceIBPC";
+ goto cp0_unimplemented;
+ case CP0_REG23__TRACEDBPC:
+ /* PDtrace support */
+ /* gen_helper_dmfc0_tracedbpc(arg, cpu_env); */
+ register_name = "TraceDBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -8863,7 +8889,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
- case 0:
+ case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
@@ -8874,35 +8900,35 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
- case 0:
+ case CP0_REG25__PERFCTL0:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Performance0));
register_name = "Performance0";
break;
- case 1:
+ case CP0_REG25__PERFCNT0:
/* gen_helper_dmfc0_performance1(arg); */
register_name = "Performance1";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG25__PERFCTL1:
/* gen_helper_dmfc0_performance2(arg); */
register_name = "Performance2";
goto cp0_unimplemented;
- case 3:
+ case CP0_REG25__PERFCNT1:
/* gen_helper_dmfc0_performance3(arg); */
register_name = "Performance3";
goto cp0_unimplemented;
- case 4:
+ case CP0_REG25__PERFCTL2:
/* gen_helper_dmfc0_performance4(arg); */
register_name = "Performance4";
goto cp0_unimplemented;
- case 5:
+ case CP0_REG25__PERFCNT2:
/* gen_helper_dmfc0_performance5(arg); */
register_name = "Performance5";
goto cp0_unimplemented;
- case 6:
+ case CP0_REG25__PERFCTL3:
/* gen_helper_dmfc0_performance6(arg); */
register_name = "Performance6";
goto cp0_unimplemented;
- case 7:
+ case CP0_REG25__PERFCNT3:
/* gen_helper_dmfc0_performance7(arg); */
register_name = "Performance7";
goto cp0_unimplemented;
@@ -8912,7 +8938,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
- case 0:
+ case CP0_REG26__ERRCTL:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_ErrCtl));
register_name = "ErrCtl";
break;
@@ -8923,10 +8949,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case CP0_REGISTER_27:
switch (sel) {
/* ignored */
- case 0:
- case 1:
- case 2:
- case 3:
+ case CP0_REG27__CACHERR:
tcg_gen_movi_tl(arg, 0); /* unimplemented */
register_name = "CacheErr";
break;
@@ -8936,17 +8959,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG28__TAGLO:
+ case CP0_REG28__TAGLO1:
+ case CP0_REG28__TAGLO2:
+ case CP0_REG28__TAGLO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagLo));
register_name = "TagLo";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG28__DATALO:
+ case CP0_REG28__DATALO1:
+ case CP0_REG28__DATALO2:
+ case CP0_REG28__DATALO3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataLo));
register_name = "DataLo";
break;
@@ -8956,17 +8979,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG29__TAGHI:
+ case CP0_REG29__TAGHI1:
+ case CP0_REG29__TAGHI2:
+ case CP0_REG29__TAGHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_TagHi));
register_name = "TagHi";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG29__DATAHI:
+ case CP0_REG29__DATAHI1:
+ case CP0_REG29__DATAHI2:
+ case CP0_REG29__DATAHI3:
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DataHi));
register_name = "DataHi";
break;
@@ -8976,7 +8999,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_30:
switch (sel) {
- case 0:
+ case CP0_REG30__ERROREPC:
tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
@@ -8986,17 +9009,17 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
- case 0:
+ case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG31__KSCRATCH1:
+ case CP0_REG31__KSCRATCH2:
+ case CP0_REG31__KSCRATCH3:
+ case CP0_REG31__KSCRATCH4:
+ case CP0_REG31__KSCRATCH5:
+ case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_ld_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
@@ -9033,26 +9056,26 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
switch (reg) {
case CP0_REGISTER_00:
switch (sel) {
- case 0:
+ case CP0_REG00__INDEX:
gen_helper_mtc0_index(cpu_env, arg);
register_name = "Index";
break;
- case 1:
+ case CP0_REG00__MVPCONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_mvpcontrol(cpu_env, arg);
register_name = "MVPControl";
break;
- case 2:
+ case CP0_REG00__MVPCONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf0";
break;
- case 3:
+ case CP0_REG00__MVPCONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
/* ignored */
register_name = "MVPConf1";
break;
- case 4:
+ case CP0_REG00__VPCONTROL:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "VPControl";
@@ -9063,41 +9086,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_01:
switch (sel) {
- case 0:
+ case CP0_REG01__RANDOM:
/* ignored */
register_name = "Random";
break;
- case 1:
+ case CP0_REG01__VPECONTROL:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpecontrol(cpu_env, arg);
register_name = "VPEControl";
break;
- case 2:
+ case CP0_REG01__VPECONF0:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf0(cpu_env, arg);
register_name = "VPEConf0";
break;
- case 3:
+ case CP0_REG01__VPECONF1:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeconf1(cpu_env, arg);
register_name = "VPEConf1";
break;
- case 4:
+ case CP0_REG01__YQMASK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_yqmask(cpu_env, arg);
register_name = "YQMask";
break;
- case 5:
+ case CP0_REG01__VPESCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
register_name = "VPESchedule";
break;
- case 6:
+ case CP0_REG01__VPESCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
register_name = "VPEScheFBack";
break;
- case 7:
+ case CP0_REG01__VPEOPT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_vpeopt(cpu_env, arg);
register_name = "VPEOpt";
@@ -9108,41 +9131,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_02:
switch (sel) {
- case 0:
+ case CP0_REG02__ENTRYLO0:
gen_helper_dmtc0_entrylo0(cpu_env, arg);
register_name = "EntryLo0";
break;
- case 1:
+ case CP0_REG02__TCSTATUS:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcstatus(cpu_env, arg);
register_name = "TCStatus";
break;
- case 2:
+ case CP0_REG02__TCBIND:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcbind(cpu_env, arg);
register_name = "TCBind";
break;
- case 3:
+ case CP0_REG02__TCRESTART:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcrestart(cpu_env, arg);
register_name = "TCRestart";
break;
- case 4:
+ case CP0_REG02__TCHALT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tchalt(cpu_env, arg);
register_name = "TCHalt";
break;
- case 5:
+ case CP0_REG02__TCCONTEXT:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tccontext(cpu_env, arg);
register_name = "TCContext";
break;
- case 6:
+ case CP0_REG02__TCSCHEDULE:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschedule(cpu_env, arg);
register_name = "TCSchedule";
break;
- case 7:
+ case CP0_REG02__TCSCHEFBACK:
CP0_CHECK(ctx->insn_flags & ASE_MT);
gen_helper_mtc0_tcschefback(cpu_env, arg);
register_name = "TCScheFBack";
@@ -9153,11 +9176,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_03:
switch (sel) {
- case 0:
+ case CP0_REG03__ENTRYLO1:
gen_helper_dmtc0_entrylo1(cpu_env, arg);
register_name = "EntryLo1";
break;
- case 1:
+ case CP0_REG03__GLOBALNUM:
CP0_CHECK(ctx->vp);
/* ignored */
register_name = "GlobalNumber";
@@ -9168,15 +9191,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_04:
switch (sel) {
- case 0:
+ case CP0_REG04__CONTEXT:
gen_helper_mtc0_context(cpu_env, arg);
register_name = "Context";
break;
- case 1:
-// gen_helper_mtc0_contextconfig(cpu_env, arg); /* SmartMIPS ASE */
+ case CP0_REG04__CONTEXTCONFIG:
+ /* SmartMIPS ASE */
+ /* gen_helper_dmtc0_contextconfig(arg); */
register_name = "ContextConfig";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG04__USERLOCAL:
CP0_CHECK(ctx->ulri);
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, active_tc.CP0_UserLocal));
@@ -9188,41 +9212,41 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_05:
switch (sel) {
- case 0:
+ case CP0_REG05__PAGEMASK:
gen_helper_mtc0_pagemask(cpu_env, arg);
register_name = "PageMask";
break;
- case 1:
+ case CP0_REG05__PAGEGRAIN:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_pagegrain(cpu_env, arg);
register_name = "PageGrain";
break;
- case 2:
+ case CP0_REG05__SEGCTL0:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl0(cpu_env, arg);
register_name = "SegCtl0";
break;
- case 3:
+ case CP0_REG05__SEGCTL1:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl1(cpu_env, arg);
register_name = "SegCtl1";
break;
- case 4:
+ case CP0_REG05__SEGCTL2:
CP0_CHECK(ctx->sc);
gen_helper_mtc0_segctl2(cpu_env, arg);
register_name = "SegCtl2";
break;
- case 5:
+ case CP0_REG05__PWBASE:
check_pw(ctx);
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_PWBase));
register_name = "PWBase";
break;
- case 6:
+ case CP0_REG05__PWFIELD:
check_pw(ctx);
gen_helper_mtc0_pwfield(cpu_env, arg);
register_name = "PWField";
break;
- case 7:
+ case CP0_REG05__PWSIZE:
check_pw(ctx);
gen_helper_mtc0_pwsize(cpu_env, arg);
register_name = "PWSize";
@@ -9233,36 +9257,36 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_06:
switch (sel) {
- case 0:
+ case CP0_REG06__WIRED:
gen_helper_mtc0_wired(cpu_env, arg);
register_name = "Wired";
break;
- case 1:
+ case CP0_REG06__SRSCONF0:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf0(cpu_env, arg);
register_name = "SRSConf0";
break;
- case 2:
+ case CP0_REG06__SRSCONF1:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf1(cpu_env, arg);
register_name = "SRSConf1";
break;
- case 3:
+ case CP0_REG06__SRSCONF2:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf2(cpu_env, arg);
register_name = "SRSConf2";
break;
- case 4:
+ case CP0_REG06__SRSCONF3:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf3(cpu_env, arg);
register_name = "SRSConf3";
break;
- case 5:
+ case CP0_REG06__SRSCONF4:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsconf4(cpu_env, arg);
register_name = "SRSConf4";
break;
- case 6:
+ case CP0_REG06__PWCTL:
check_pw(ctx);
gen_helper_mtc0_pwctl(cpu_env, arg);
register_name = "PWCtl";
@@ -9273,7 +9297,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_07:
switch (sel) {
- case 0:
+ case CP0_REG07__HWRENA:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_hwrena(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
@@ -9285,19 +9309,19 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_08:
switch (sel) {
- case 0:
+ case CP0_REG08__BADVADDR:
/* ignored */
register_name = "BadVAddr";
break;
- case 1:
+ case CP0_REG08__BADINSTR:
/* ignored */
register_name = "BadInstr";
break;
- case 2:
+ case CP0_REG08__BADINSTRP:
/* ignored */
register_name = "BadInstrP";
break;
- case 3:
+ case CP0_REG08__BADINSTRX:
/* ignored */
register_name = "BadInstrX";
break;
@@ -9307,16 +9331,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_09:
switch (sel) {
- case 0:
+ case CP0_REG09__COUNT:
gen_helper_mtc0_count(cpu_env, arg);
register_name = "Count";
break;
- case 6:
+ case CP0_REG09__SAARI:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saari(cpu_env, arg);
register_name = "SAARI";
break;
- case 7:
+ case CP0_REG09__SAAR:
CP0_CHECK(ctx->saar);
gen_helper_mtc0_saar(cpu_env, arg);
register_name = "SAAR";
@@ -9329,7 +9353,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_10:
switch (sel) {
- case 0:
+ case CP0_REG10__ENTRYHI:
gen_helper_mtc0_entryhi(cpu_env, arg);
register_name = "EntryHi";
break;
@@ -9339,7 +9363,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_11:
switch (sel) {
- case 0:
+ case CP0_REG11__COMPARE:
gen_helper_mtc0_compare(cpu_env, arg);
register_name = "Compare";
break;
@@ -9352,7 +9376,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_12:
switch (sel) {
- case 0:
+ case CP0_REG12__STATUS:
save_cpu_state(ctx, 1);
gen_helper_mtc0_status(cpu_env, arg);
/* DISAS_STOP isn't good enough here, hflags may have changed. */
@@ -9360,21 +9384,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Status";
break;
- case 1:
+ case CP0_REG12__INTCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_intctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "IntCtl";
break;
- case 2:
+ case CP0_REG12__SRSCTL:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_srsctl(cpu_env, arg);
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "SRSCtl";
break;
- case 3:
+ case CP0_REG12__SRSMAP:
check_insn(ctx, ISA_MIPS32R2);
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
/* Stop translation as we may have switched the execution mode */
@@ -9387,7 +9411,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_13:
switch (sel) {
- case 0:
+ case CP0_REG13__CAUSE:
save_cpu_state(ctx, 1);
gen_helper_mtc0_cause(cpu_env, arg);
/*
@@ -9405,7 +9429,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_14:
switch (sel) {
- case 0:
+ case CP0_REG14__EPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC));
register_name = "EPC";
break;
@@ -9415,11 +9439,11 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_15:
switch (sel) {
- case 0:
+ case CP0_REG15__PRID:
/* ignored */
register_name = "PRid";
break;
- case 1:
+ case CP0_REG15__EBASE:
check_insn(ctx, ISA_MIPS32R2);
gen_helper_mtc0_ebase(cpu_env, arg);
register_name = "EBase";
@@ -9430,33 +9454,33 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_16:
switch (sel) {
- case 0:
+ case CP0_REG16__CONFIG:
gen_helper_mtc0_config0(cpu_env, arg);
register_name = "Config";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 1:
+ case CP0_REG16__CONFIG1:
/* ignored, read only */
register_name = "Config1";
break;
- case 2:
+ case CP0_REG16__CONFIG2:
gen_helper_mtc0_config2(cpu_env, arg);
register_name = "Config2";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 3:
+ case CP0_REG16__CONFIG3:
gen_helper_mtc0_config3(cpu_env, arg);
register_name = "Config3";
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
break;
- case 4:
+ case CP0_REG16__CONFIG4:
/* currently ignored */
register_name = "Config4";
break;
- case 5:
+ case CP0_REG16__CONFIG5:
gen_helper_mtc0_config5(cpu_env, arg);
register_name = "Config5";
/* Stop translation as we may have switched the execution mode */
@@ -9470,16 +9494,16 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_17:
switch (sel) {
- case 0:
+ case CP0_REG17__LLADDR:
gen_helper_mtc0_lladdr(cpu_env, arg);
register_name = "LLAddr";
break;
- case 1:
+ case CP0_REG17__MAAR:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maar(cpu_env, arg);
register_name = "MAAR";
break;
- case 2:
+ case CP0_REG17__MAARI:
CP0_CHECK(ctx->mrp);
gen_helper_mtc0_maari(cpu_env, arg);
register_name = "MAARI";
@@ -9490,14 +9514,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_18:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG18__WATCHLO0:
+ case CP0_REG18__WATCHLO1:
+ case CP0_REG18__WATCHLO2:
+ case CP0_REG18__WATCHLO3:
+ case CP0_REG18__WATCHLO4:
+ case CP0_REG18__WATCHLO5:
+ case CP0_REG18__WATCHLO6:
+ case CP0_REG18__WATCHLO7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchlo, arg, sel);
register_name = "WatchLo";
@@ -9508,14 +9532,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_19:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG19__WATCHHI0:
+ case CP0_REG19__WATCHHI1:
+ case CP0_REG19__WATCHHI2:
+ case CP0_REG19__WATCHHI3:
+ case CP0_REG19__WATCHHI4:
+ case CP0_REG19__WATCHHI5:
+ case CP0_REG19__WATCHHI6:
+ case CP0_REG19__WATCHHI7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(mtc0_watchhi, arg, sel);
register_name = "WatchHi";
@@ -9526,7 +9550,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_20:
switch (sel) {
- case 0:
+ case CP0_REG20__XCONTEXT:
check_insn(ctx, ISA_MIPS3);
gen_helper_mtc0_xcontext(cpu_env, arg);
register_name = "XContext";
@@ -9553,36 +9577,47 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_23:
switch (sel) {
- case 0:
+ case CP0_REG23__DEBUG:
gen_helper_mtc0_debug(cpu_env, arg); /* EJTAG support */
/* DISAS_STOP isn't good enough here, hflags may have changed. */
gen_save_pc(ctx->base.pc_next + 4);
ctx->base.is_jmp = DISAS_EXIT;
register_name = "Debug";
break;
- case 1:
-// gen_helper_mtc0_tracecontrol(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracecontrol(cpu_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceControl";
goto cp0_unimplemented;
- case 2:
-// gen_helper_mtc0_tracecontrol2(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACECONTROL2:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracecontrol2(cpu_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
register_name = "TraceControl2";
goto cp0_unimplemented;
- case 3:
-// gen_helper_mtc0_usertracedata(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__USERTRACEDATA1:
+ /* PDtrace support */
+ /* gen_helper_mtc0_usertracedata1(cpu_env, arg);*/
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- register_name = "UserTraceData";
+ register_name = "UserTraceData1";
goto cp0_unimplemented;
- case 4:
-// gen_helper_mtc0_tracebpc(cpu_env, arg); /* PDtrace support */
+ case CP0_REG23__TRACEIBPC:
+ /* PDtrace support */
+ /* gen_helper_mtc0_traceibpc(cpu_env, arg); */
/* Stop translation as we may have switched the execution mode */
ctx->base.is_jmp = DISAS_STOP;
- register_name = "TraceBPC";
+ register_name = "TraceIBPC";
+ goto cp0_unimplemented;
+ case CP0_REG23__TRACEDBPC:
+ /* PDtrace support */
+ /* gen_helper_mtc0_tracedbpc(cpu_env, arg); */
+ /* Stop translation as we may have switched the execution mode */
+ ctx->base.is_jmp = DISAS_STOP;
+ register_name = "TraceDBPC";
goto cp0_unimplemented;
default:
goto cp0_unimplemented;
@@ -9590,7 +9625,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_24:
switch (sel) {
- case 0:
+ case CP0_REG24__DEPC:
/* EJTAG support */
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC));
register_name = "DEPC";
@@ -9601,35 +9636,35 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_25:
switch (sel) {
- case 0:
+ case CP0_REG25__PERFCTL0:
gen_helper_mtc0_performance0(cpu_env, arg);
register_name = "Performance0";
break;
- case 1:
+ case CP0_REG25__PERFCNT0:
/* gen_helper_mtc0_performance1(cpu_env, arg); */
register_name = "Performance1";
goto cp0_unimplemented;
- case 2:
+ case CP0_REG25__PERFCTL1:
/* gen_helper_mtc0_performance2(cpu_env, arg); */
register_name = "Performance2";
goto cp0_unimplemented;
- case 3:
+ case CP0_REG25__PERFCNT1:
/* gen_helper_mtc0_performance3(cpu_env, arg); */
register_name = "Performance3";
goto cp0_unimplemented;
- case 4:
+ case CP0_REG25__PERFCTL2:
/* gen_helper_mtc0_performance4(cpu_env, arg); */
register_name = "Performance4";
goto cp0_unimplemented;
- case 5:
+ case CP0_REG25__PERFCNT2:
/* gen_helper_mtc0_performance5(cpu_env, arg); */
register_name = "Performance5";
goto cp0_unimplemented;
- case 6:
+ case CP0_REG25__PERFCTL3:
/* gen_helper_mtc0_performance6(cpu_env, arg); */
register_name = "Performance6";
goto cp0_unimplemented;
- case 7:
+ case CP0_REG25__PERFCNT3:
/* gen_helper_mtc0_performance7(cpu_env, arg); */
register_name = "Performance7";
goto cp0_unimplemented;
@@ -9639,7 +9674,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_26:
switch (sel) {
- case 0:
+ case CP0_REG26__ERRCTL:
gen_helper_mtc0_errctl(cpu_env, arg);
ctx->base.is_jmp = DISAS_STOP;
register_name = "ErrCtl";
@@ -9650,10 +9685,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_27:
switch (sel) {
- case 0:
- case 1:
- case 2:
- case 3:
+ case CP0_REG27__CACHERR:
/* ignored */
register_name = "CacheErr";
break;
@@ -9663,17 +9695,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_28:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG28__TAGLO:
+ case CP0_REG28__TAGLO1:
+ case CP0_REG28__TAGLO2:
+ case CP0_REG28__TAGLO3:
gen_helper_mtc0_taglo(cpu_env, arg);
register_name = "TagLo";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG28__DATALO:
+ case CP0_REG28__DATALO1:
+ case CP0_REG28__DATALO2:
+ case CP0_REG28__DATALO3:
gen_helper_mtc0_datalo(cpu_env, arg);
register_name = "DataLo";
break;
@@ -9683,17 +9715,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_29:
switch (sel) {
- case 0:
- case 2:
- case 4:
- case 6:
+ case CP0_REG29__TAGHI:
+ case CP0_REG29__TAGHI1:
+ case CP0_REG29__TAGHI2:
+ case CP0_REG29__TAGHI3:
gen_helper_mtc0_taghi(cpu_env, arg);
register_name = "TagHi";
break;
- case 1:
- case 3:
- case 5:
- case 7:
+ case CP0_REG29__DATAHI:
+ case CP0_REG29__DATAHI1:
+ case CP0_REG29__DATAHI2:
+ case CP0_REG29__DATAHI3:
gen_helper_mtc0_datahi(cpu_env, arg);
register_name = "DataHi";
break;
@@ -9704,7 +9736,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_30:
switch (sel) {
- case 0:
+ case CP0_REG30__ERROREPC:
tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC));
register_name = "ErrorEPC";
break;
@@ -9714,17 +9746,17 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
break;
case CP0_REGISTER_31:
switch (sel) {
- case 0:
+ case CP0_REG31__DESAVE:
/* EJTAG support */
gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_DESAVE));
register_name = "DESAVE";
break;
- case 2:
- case 3:
- case 4:
- case 5:
- case 6:
- case 7:
+ case CP0_REG31__KSCRATCH1:
+ case CP0_REG31__KSCRATCH2:
+ case CP0_REG31__KSCRATCH3:
+ case CP0_REG31__KSCRATCH4:
+ case CP0_REG31__KSCRATCH5:
+ case CP0_REG31__KSCRATCH6:
CP0_CHECK(ctx->kscrexist & (1 << sel));
tcg_gen_st_tl(arg, cpu_env,
offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
generated by cgit v1.2.3 (git 2.26.2) at 2025-01-14 10:22:51 +0000