diff options
author | Peter Maydell <peter.maydell@linaro.org> | 2018-05-21 09:44:37 +0100 |
---|---|---|
committer | Peter Maydell <peter.maydell@linaro.org> | 2018-05-21 09:44:37 +0100 |
commit | dfa93a0b6ef51fd8e0285a9991704b51cf884c33 (patch) | |
tree | c6da491a939f3419a7a4246b8e53da8af74ff423 | |
parent | 5bcf917ee37a5efbef99f091a96db54a5276becb (diff) | |
parent | f29c0b170fa9e0568f2d02e764e18b00cad3a27f (diff) |
Merge remote-tracking branch 'remotes/rth/tags/pull-fpu-20180518' into staging
Honor CPU_DUMP_FPU
# gpg: Signature made Fri 18 May 2018 22:56:12 BST
# gpg: using RSA key 64DF38E8AF7E215F
# gpg: Good signature from "Richard Henderson <richard.henderson@linaro.org>"
# Primary key fingerprint: 7A48 1E78 868B 4DB6 A85A 05C0 64DF 38E8 AF7E 215F
* remotes/rth/tags/pull-fpu-20180518:
target/xtensa: Honor CPU_DUMP_FPU
target/unicore32: Honor CPU_DUMP_FPU
target/sparc: Honor CPU_DUMP_FPU
target/s390x: Honor CPU_DUMP_FPU
target/riscv: Honor CPU_DUMP_FPU
target/ppc: Honor CPU_DUMP_FPU
target/mips: Honor CPU_DUMP_FPU
target/alpha: Honor CPU_DUMP_FPU
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-rw-r--r-- | target/alpha/helper.c | 17 | ||||
-rw-r--r-- | target/mips/translate.c | 3 | ||||
-rw-r--r-- | target/ppc/translate.c | 20 | ||||
-rw-r--r-- | target/riscv/cpu.c | 12 | ||||
-rw-r--r-- | target/s390x/helper.c | 23 | ||||
-rw-r--r-- | target/sparc/cpu.c | 17 | ||||
-rw-r--r-- | target/unicore32/translate.c | 4 | ||||
-rw-r--r-- | target/xtensa/translate.c | 3 |
8 files changed, 57 insertions, 42 deletions
diff --git a/target/alpha/helper.c b/target/alpha/helper.c index 8a6a948572..57e2c212b3 100644 --- a/target/alpha/helper.c +++ b/target/alpha/helper.c @@ -442,20 +442,19 @@ void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, cpu_fprintf(f, " PC " TARGET_FMT_lx " PS %02x\n", env->pc, extract32(env->flags, ENV_FLAG_PS_SHIFT, 8)); for (i = 0; i < 31; i++) { - cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx " ", i, - linux_reg_names[i], cpu_alpha_load_gr(env, i)); - if ((i % 3) == 2) - cpu_fprintf(f, "\n"); + cpu_fprintf(f, "IR%02d %s " TARGET_FMT_lx "%c", i, + linux_reg_names[i], cpu_alpha_load_gr(env, i), + (i % 3) == 2 ? '\n' : ' '); } cpu_fprintf(f, "lock_a " TARGET_FMT_lx " lock_v " TARGET_FMT_lx "\n", env->lock_addr, env->lock_value); - for (i = 0; i < 31; i++) { - cpu_fprintf(f, "FIR%02d " TARGET_FMT_lx " ", i, - *((uint64_t *)(&env->fir[i]))); - if ((i % 3) == 2) - cpu_fprintf(f, "\n"); + if (flags & CPU_DUMP_FPU) { + for (i = 0; i < 31; i++) { + cpu_fprintf(f, "FIR%02d %016" PRIx64 "%c", i, env->fir[i], + (i % 3) == 2 ? '\n' : ' '); + } } cpu_fprintf(f, "\n"); } diff --git a/target/mips/translate.c b/target/mips/translate.c index f1c1fdd35c..e88f983ae7 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -20446,8 +20446,9 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, env->CP0_Config2, env->CP0_Config3); cpu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", env->CP0_Config4, env->CP0_Config5); - if (env->hflags & MIPS_HFLAG_FPU) + if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { fpu_dump_state(env, f, cpu_fprintf, flags); + } } void mips_tcg_init(void) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index d5e5f953da..e30d99fcbc 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7048,14 +7048,20 @@ void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, } cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n", env->reserve_addr); - for (i = 0; i < 32; i++) { - if ((i & (RFPL - 1)) == 0) - cpu_fprintf(f, "FPR%02d", i); - cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); - if ((i & (RFPL - 1)) == (RFPL - 1)) - cpu_fprintf(f, "\n"); + + if (flags & CPU_DUMP_FPU) { + for (i = 0; i < 32; i++) { + if ((i & (RFPL - 1)) == 0) { + cpu_fprintf(f, "FPR%02d", i); + } + cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i])); + if ((i & (RFPL - 1)) == (RFPL - 1)) { + cpu_fprintf(f, "\n"); + } + } + cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); } - cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr); + #if !defined(CONFIG_USER_ONLY) cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n", diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 4e5a56d4e3..d630e8fd6c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -219,11 +219,13 @@ static void riscv_cpu_dump_state(CPUState *cs, FILE *f, cpu_fprintf(f, "\n"); } } - for (i = 0; i < 32; i++) { - cpu_fprintf(f, " %s %016" PRIx64, - riscv_fpr_regnames[i], env->fpr[i]); - if ((i & 3) == 3) { - cpu_fprintf(f, "\n"); + if (flags & CPU_DUMP_FPU) { + for (i = 0; i < 32; i++) { + cpu_fprintf(f, " %s %016" PRIx64, + riscv_fpr_regnames[i], env->fpr[i]); + if ((i & 3) == 3) { + cpu_fprintf(f, "\n"); + } } } } diff --git a/target/s390x/helper.c b/target/s390x/helper.c index e8548f340a..fd5791f134 100644 --- a/target/s390x/helper.c +++ b/target/s390x/helper.c @@ -327,21 +327,22 @@ void s390_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, } } - for (i = 0; i < 16; i++) { - cpu_fprintf(f, "F%02d=%016" PRIx64, i, get_freg(env, i)->ll); - if ((i % 4) == 3) { - cpu_fprintf(f, "\n"); + if (flags & CPU_DUMP_FPU) { + if (s390_has_feat(S390_FEAT_VECTOR)) { + for (i = 0; i < 32; i++) { + cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64 "%c", + i, env->vregs[i][0].ll, env->vregs[i][1].ll, + i % 2 ? '\n' : ' '); + } } else { - cpu_fprintf(f, " "); + for (i = 0; i < 16; i++) { + cpu_fprintf(f, "F%02d=%016" PRIx64 "%c", + i, get_freg(env, i)->ll, + (i % 4) == 3 ? '\n' : ' '); + } } } - for (i = 0; i < 32; i++) { - cpu_fprintf(f, "V%02d=%016" PRIx64 "%016" PRIx64, i, - env->vregs[i][0].ll, env->vregs[i][1].ll); - cpu_fprintf(f, (i % 2) ? "\n" : " "); - } - #ifndef CONFIG_USER_ONLY for (i = 0; i < 16; i++) { cpu_fprintf(f, "C%02d=%016" PRIx64, i, env->cregs[i]); diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index ff6ed91f9a..0f090ece54 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -647,15 +647,18 @@ void sparc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, } } - for (i = 0; i < TARGET_DPREGS; i++) { - if ((i & 3) == 0) { - cpu_fprintf(f, "%%f%02d: ", i * 2); - } - cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll); - if ((i & 3) == 3) { - cpu_fprintf(f, "\n"); + if (flags & CPU_DUMP_FPU) { + for (i = 0; i < TARGET_DPREGS; i++) { + if ((i & 3) == 0) { + cpu_fprintf(f, "%%f%02d: ", i * 2); + } + cpu_fprintf(f, " %016" PRIx64, env->fpr[i].ll); + if ((i & 3) == 3) { + cpu_fprintf(f, "\n"); + } } } + #ifdef TARGET_SPARC64 cpu_fprintf(f, "pstate: %08x ccr: %02x (icc: ", env->pstate, (unsigned)cpu_get_ccr(env)); diff --git a/target/unicore32/translate.c b/target/unicore32/translate.c index abe2ea8592..3cae111955 100644 --- a/target/unicore32/translate.c +++ b/target/unicore32/translate.c @@ -2101,7 +2101,9 @@ void uc32_cpu_dump_state(CPUState *cs, FILE *f, psr & (1 << 28) ? 'V' : '-', cpu_mode_names[psr & 0xf]); - cpu_dump_state_ucf64(env, f, cpu_fprintf, flags); + if (flags & CPU_DUMP_FPU) { + cpu_dump_state_ucf64(env, f, cpu_fprintf, flags); + } } void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb, diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index ae0feb0254..53f6f5db8f 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1243,7 +1243,8 @@ void xtensa_cpu_dump_state(CPUState *cs, FILE *f, } } - if (xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) { + if ((flags & CPU_DUMP_FPU) && + xtensa_option_enabled(env->config, XTENSA_OPTION_FP_COPROCESSOR)) { cpu_fprintf(f, "\n"); for (i = 0; i < 16; ++i) { |