diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2012-11-14 15:04:42 +0100 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2012-11-15 14:37:55 +0100 |
| commit | 68d001928b151a0c50f367c0bdca645b3d5e9ed3 (patch) | |
| tree | a24065d5220d42e15c16bc0f4846ef56c735d28a | |
| parent | ce34cf72fe508b27a78f83c184142e8d1e6a048a (diff) | |
mips/malta: fix CBUS UART interrupt pin
According to the MIPS Malta Developement Platform User's Manual, the
i8259 interrupt controller is supposed to be connected to the hardware
IRQ0, and the CBUS UART to the hardware interrupt 2.
In QEMU they are both connected to hardware interrupt 0, the CBUS UART
interrupt being wrong. This patch fixes that. It should be noted that
the irq array in QEMU includes the software interrupts, hence
env->irq[2] is the first hardware interrupt.
Cc: Ralf Baechle <ralf@linux-mips.org>
Reviewed-by: Eric Johnson <ericj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| -rw-r--r-- | hw/mips_malta.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/hw/mips_malta.c b/hw/mips_malta.c index 0571d58908..4d2464a02c 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -861,7 +861,8 @@ void mips_malta_init(QEMUMachineInitArgs *args) be = 0; #endif /* FPGA */ - malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[2], serial_hds[2]); + /* The CBUS UART is attached to the MIPS CPU INT2 pin, ie interrupt 4 */ + malta_fpga_init(system_memory, FPGA_ADDRESS, env->irq[4], serial_hds[2]); /* Load firmware in flash / BIOS. */ dinfo = drive_get(IF_PFLASH, 0, fl_idx); |