diff options
| author | Peter Crosthwaite <peter.crosthwaite@xilinx.com> | 2014-08-29 15:00:29 +0100 |
|---|---|---|
| committer | Peter Maydell <peter.maydell@linaro.org> | 2014-08-29 15:00:29 +0100 |
| commit | 421c7ebd93d33a3276b78985b9e25cfea35692f0 (patch) | |
| tree | bc52e8042f0d042c93e0aa765b0410e24f90abc8 | |
| parent | c92c06872a092eaba64ea7e56ceff762be48b093 (diff) | |
arm: Implement PMCCNTR 32b read-modify-write
The register is now 64bit, however a 32 bit write to the register
should leave the higher bits unchanged. The open coded write handler
does not implement this, so we need to read-modify-write accordingly.
Signed-off-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Reviewed-by: Alistair Francis <alistair23@gmail.com>
Message-id: ec350573424bb2adc1701c3b9278d26598e2f2d1.1409025949.git.peter.crosthwaite@xilinx.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
| -rw-r--r-- | target-arm/helper.c | 11 |
1 files changed, 10 insertions, 1 deletions
diff --git a/target-arm/helper.c b/target-arm/helper.c index 711ca12b12..0d2ee41337 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -623,6 +623,15 @@ static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri, } env->cp15.c15_ccnt = total_ticks - value; } + +static void pmccntr_write32(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t cur_val = pmccntr_read(env, NULL); + + pmccntr_write(env, ri, deposit64(cur_val, 0, 32, value)); +} + #endif static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -754,7 +763,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = { #ifndef CONFIG_USER_ONLY { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0, .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO, - .readfn = pmccntr_read, .writefn = pmccntr_write, + .readfn = pmccntr_read, .writefn = pmccntr_write32, .accessfn = pmreg_access }, #endif { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1, |