diff options
| author | James Hogan <james.hogan@imgtec.com> | 2017-07-31 14:36:45 +0100 |
|---|---|---|
| committer | Yongbok Kim <yongbok.kim@imgtec.com> | 2017-08-02 17:01:27 +0100 |
| commit | cb539fd241900f51de7d21244f7a55422ad0d40a (patch) | |
| tree | 23aaedd50316634e5cd0cacc90e009caf0d8a025 | |
| parent | aaaec6acad7cf97372d48c1b09126a09697519c8 (diff) | |
target-mips: Don't stop on [d]mtc0 DESAVE/KScratch
Writing to the MIPS DESAVE register (and now the KScratch registers)
will stop translation, supposedly due to risk of execution mode
switches. However these registers are basically RW scratch registers
with no side effects so there is no risk of them triggering execution
mode changes.
Drop the bstate = BS_STOP for these registers for both mtc0 and dmtc0.
Fixes: 7a387fffce50 ("Add MIPS32R2 instructions, and generally straighten out the instruction decoding. This is also the first percent towards MIPS64 support.")
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Aurelien Jarno <aurelien@aurel32.net>
Cc: Yongbok Kim <yongbok.kim@imgtec.com>
Reviewed-by: Yongbok Kim <yongbok.kim@imgtec.com>
Signed-off-by: Yongbok Kim <yongbok.kim@imgtec.com>
| -rw-r--r-- | target/mips/translate.c | 4 |
1 files changed, 0 insertions, 4 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 51626aead3..0bca700fb3 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -6386,8 +6386,6 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) default: goto cp0_unimplemented; } - /* Stop translation as we may have switched the execution mode */ - ctx->bstate = BS_STOP; break; default: goto cp0_unimplemented; @@ -7714,8 +7712,6 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel) default: goto cp0_unimplemented; } - /* Stop translation as we may have switched the execution mode */ - ctx->bstate = BS_STOP; break; default: goto cp0_unimplemented; |