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authorAndreas Färber <afaerber@suse.de>2012-04-03 00:00:17 +0200
committerAndreas Färber <afaerber@suse.de>2012-04-10 17:10:27 +0200
commitde024815e3b523addf58f1f79846b7fe74643678 (patch)
tree20ecd213f8ba6e789def7396c4a31e433714b802
parent5fd2087a1b7b3075828de741d76188441ee35bc8 (diff)
target-i386: QOM'ify CPU init
Move code from cpu_x86_init() to new QOM x86_cpu_initfn(). Also move mce_init() to cpu.c since it's used nowhere else. Signed-off-by: Andreas Färber <afaerber@suse.de>
-rw-r--r--target-i386/cpu.c27
-rw-r--r--target-i386/helper.c18
2 files changed, 27 insertions, 18 deletions
diff --git a/target-i386/cpu.c b/target-i386/cpu.c
index 36790da947..f4463e18dc 100644
--- a/target-i386/cpu.c
+++ b/target-i386/cpu.c
@@ -1380,6 +1380,32 @@ static void x86_cpu_reset(CPUState *s)
cpu_state_reset(env);
}
+static void mce_init(X86CPU *cpu)
+{
+ CPUX86State *cenv = &cpu->env;
+ unsigned int bank;
+
+ if (((cenv->cpuid_version >> 8) & 0xf) >= 6
+ && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
+ (CPUID_MCE | CPUID_MCA)) {
+ cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
+ cenv->mcg_ctl = ~(uint64_t)0;
+ for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
+ cenv->mce_banks[bank * 4] = ~(uint64_t)0;
+ }
+ }
+}
+
+static void x86_cpu_initfn(Object *obj)
+{
+ X86CPU *cpu = X86_CPU(obj);
+ CPUX86State *env = &cpu->env;
+
+ cpu_exec_init(env);
+ env->cpuid_apic_id = env->cpu_index;
+ mce_init(cpu);
+}
+
static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
{
X86CPUClass *xcc = X86_CPU_CLASS(oc);
@@ -1393,6 +1419,7 @@ static const TypeInfo x86_cpu_type_info = {
.name = TYPE_X86_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(X86CPU),
+ .instance_init = x86_cpu_initfn,
.abstract = false,
.class_size = sizeof(X86CPUClass),
.class_init = x86_cpu_common_class_init,
diff --git a/target-i386/helper.c b/target-i386/helper.c
index fb87975af2..d8ceee1541 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1197,21 +1197,6 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access)
}
#endif /* !CONFIG_USER_ONLY */
-static void mce_init(CPUX86State *cenv)
-{
- unsigned int bank;
-
- if (((cenv->cpuid_version >> 8) & 0xf) >= 6
- && (cenv->cpuid_features & (CPUID_MCE | CPUID_MCA)) ==
- (CPUID_MCE | CPUID_MCA)) {
- cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
- cenv->mcg_ctl = ~(uint64_t)0;
- for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
- cenv->mce_banks[bank * 4] = ~(uint64_t)0;
- }
- }
-}
-
int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector,
target_ulong *base, unsigned int *limit,
unsigned int *flags)
@@ -1249,7 +1234,6 @@ CPUX86State *cpu_x86_init(const char *cpu_model)
cpu = X86_CPU(object_new(TYPE_X86_CPU));
env = &cpu->env;
- cpu_exec_init(env);
env->cpu_model_str = cpu_model;
/* init various static tables used in TCG mode */
@@ -1265,8 +1249,6 @@ CPUX86State *cpu_x86_init(const char *cpu_model)
object_delete(OBJECT(cpu));
return NULL;
}
- env->cpuid_apic_id = env->cpu_index;
- mce_init(env);
qemu_init_vcpu(env);