diff options
| author | Aurelien Jarno <aurelien@aurel32.net> | 2010-04-09 20:52:48 +0200 |
|---|---|---|
| committer | Aurelien Jarno <aurelien@aurel32.net> | 2010-04-19 07:02:53 +0200 |
| commit | e4a7d5e88c361040a64a0f298d666a273dc6db85 (patch) | |
| tree | 646192ffb20f51e0b9dc29bc48e1e950198a6427 | |
| parent | 39221a82be8d224e935bdba10ce108a1a808a52f (diff) | |
tcg/arm: explicitely list clobbered/reserved regs
Instead of writing very compact code, declare all registers that are
clobbered or reserved one by one. This makes the code easier to read.
Also declare all the 16 registers to TCG, and mark pc as reserved.
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
| -rw-r--r-- | tcg/arm/tcg-target.c | 13 | ||||
| -rw-r--r-- | tcg/arm/tcg-target.h | 3 |
2 files changed, 11 insertions, 5 deletions
diff --git a/tcg/arm/tcg-target.c b/tcg/arm/tcg-target.c index e86ed9aeea..35f6c473b1 100644 --- a/tcg/arm/tcg-target.c +++ b/tcg/arm/tcg-target.c @@ -39,6 +39,7 @@ static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { "%r12", "%r13", "%r14", + "%pc", }; #endif @@ -1580,15 +1581,19 @@ void tcg_target_init(TCGContext *s) tcg_abort(); #endif - tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, - ((2 << TCG_REG_R14) - 1) & ~(1 << TCG_REG_R8)); + tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0, 0xffff); tcg_regset_set32(tcg_target_call_clobber_regs, 0, - ((2 << TCG_REG_R3) - 1) | - (1 << TCG_REG_R12) | (1 << TCG_REG_R14)); + (1 << TCG_REG_R0) | + (1 << TCG_REG_R1) | + (1 << TCG_REG_R2) | + (1 << TCG_REG_R3) | + (1 << TCG_REG_R12) | + (1 << TCG_REG_R14)); tcg_regset_clear(s->reserved_regs); tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK); tcg_regset_set_reg(s->reserved_regs, TCG_REG_R8); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_PC); tcg_add_target_add_op_defs(arm_op_defs); } diff --git a/tcg/arm/tcg-target.h b/tcg/arm/tcg-target.h index 6d58de81b0..a0027b5781 100644 --- a/tcg/arm/tcg-target.h +++ b/tcg/arm/tcg-target.h @@ -44,9 +44,10 @@ enum { TCG_REG_R12, TCG_REG_R13, TCG_REG_R14, + TCG_REG_PC, }; -#define TCG_TARGET_NB_REGS 15 +#define TCG_TARGET_NB_REGS 16 #define TCG_CT_CONST_ARM 0x100 |